FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
Fuente:
arXiv
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| Main Authors: | Tong, Jianming, Itagi, Anirudh, Chatarasi, Prasanth, Krishna, Tushar |
|---|---|
| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | |
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