Fully parallel implementation of digital memcomputing on FPGA
Fuente:
arXiv
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| Autori principali: | , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866916717659160576 |
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| author | Nguyen, Dyk Chung Pershin, Yuriy V. |
| author_facet | Nguyen, Dyk Chung Pershin, Yuriy V. |
| contents | We present a fully parallel digital memcomputing solver implemented on a field-programmable gate array (FPGA) board. For this purpose, we have designed an FPGA code that solves the ordinary differential equations associated with digital memcomputing in parallel. A feature of the code is the use of only integer-type variables and integer constants to enhance optimization. Consequently, each integration step in our solver is executed in 96~ns. This method was utilized for difficult instances of the Boolean satisfiability (SAT) problem close to a phase transition, involving up to about 150 variables. Our results demonstrate that the parallel implementation reduces the scaling exponent by about 1 compared to a sequential C++ code on a standard computer. Additionally, compared to C++ code, we observed a time-to-solution advantage of about three orders of magnitude. Given the limitations of FPGA resources, the current implementation of digital memcomputing will be especially useful for solving compact but challenging problems. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2405_14442 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Fully parallel implementation of digital memcomputing on FPGA Nguyen, Dyk Chung Pershin, Yuriy V. Emerging Technologies Chaotic Dynamics We present a fully parallel digital memcomputing solver implemented on a field-programmable gate array (FPGA) board. For this purpose, we have designed an FPGA code that solves the ordinary differential equations associated with digital memcomputing in parallel. A feature of the code is the use of only integer-type variables and integer constants to enhance optimization. Consequently, each integration step in our solver is executed in 96~ns. This method was utilized for difficult instances of the Boolean satisfiability (SAT) problem close to a phase transition, involving up to about 150 variables. Our results demonstrate that the parallel implementation reduces the scaling exponent by about 1 compared to a sequential C++ code on a standard computer. Additionally, compared to C++ code, we observed a time-to-solution advantage of about three orders of magnitude. Given the limitations of FPGA resources, the current implementation of digital memcomputing will be especially useful for solving compact but challenging problems. |
| title | Fully parallel implementation of digital memcomputing on FPGA |
| topic | Emerging Technologies Chaotic Dynamics |
| url | https://arxiv.org/abs/2405.14442 |