Cover Image

TrojanForge: Generating Adversarial Hardware Trojan Examples Using Reinforcement Learning

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Sarihi, Amin, Jamieson, Peter, Patooghy, Ahmad, Badawy, Abdel-Hameed A.
Format:	Preprint
Published:	2024
Subjects:	Cryptography and Security Hardware Architecture Machine Learning B.8.1
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Trojan Playground: A Reinforcement Learning Framework for Hardware Trojan Insertion and Detection
by: Sarihi, Amin, et al.
Published: (2023)

The Seeker's Dilemma: Realistic Formulation and Benchmarking for Hardware Trojan Detection
by: Sarihi, Amin, et al.
Published: (2024)

Hiding in Plain Sight: Reframing Hardware Trojan Benchmarking as a Hide&Seek Modification
by: Sarihi, Amin, et al.
Published: (2024)

iThermTroj: Exploiting Intermittent Thermal Trojans in Multi-Processor System-on-Chips
by: Elahi, Mehdi, et al.
Published: (2025)

MATTER: Multi-stage Adaptive Thermal Trojan for Efficiency & Resilience degradation
by: Elahi, Mehdi, et al.
Published: (2024)

TrojanWhisper: Evaluating Pre-trained LLMs to Detect and Localize Hardware Trojans
by: Faruque, Md Omar, et al.
Published: (2024)

Evasive Hardware Trojan through Adversarial Power Trace
by: Omidi, Behnam, et al.
Published: (2024)

Unleashing GHOST: An LLM-Powered Framework for Automated Hardware Trojan Design
by: Faruque, Md Omar, et al.
Published: (2024)

TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
by: Sreekumar, Saideep, et al.
Published: (2026)

TroLL: Exploiting Structural Similarities between Logic Locking and Hardware Trojans
by: Liu, Yuntao, et al.
Published: (2023)

SCARF: Securing Chips with a Robust Framework against Fabrication-time Hardware Trojans
by: Eslami, Mohammad, et al.
Published: (2024)

Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms
by: Paul, Rourab, et al.
Published: (2026)

TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans
by: Wang, Fangzhou, et al.
Published: (2024)

SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions
by: Bhandari, Jitendra, et al.
Published: (2024)

Cluster-BPI: Efficient Fine-Grain Blind Power Identification for Defending against Hardware Thermal Trojans in Multicore SoCs
by: Elshamy, Mohamed R., et al.
Published: (2024)

History-Aware Trajectory k-Anonymization Using an FPGA-Based Hardware Accelerator for Real-Time Location Services
by: Nakano, Hiroshi, et al.
Published: (2025)

Security Properties for Open-Source Hardware Designs
by: Rogers, Jayden, et al.
Published: (2024)

Efficient and Lightweight In-memory Computing Architecture for Hardware Security
by: Ajmi, Hala, et al.
Published: (2022)

Modern Hardware Security: A Review of Attacks and Countermeasures
by: Mishra, Jyotiprakash, et al.
Published: (2025)

Bridging the Gap between Hardware Fuzzing and Industrial Verification
by: Ma, Ruiyang, et al.
Published: (2025)

Presto: Hardware Acceleration of Ciphers for Hybrid Homomorphic Encryption
by: Jeon, Yeonsoo, et al.
Published: (2025)

Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip
by: Mulhem, Saleh, et al.
Published: (2024)

High-Security Hardware Module with PUF and Hybrid Cryptography for Data Security
by: Amael, Joshua Tito, et al.
Published: (2024)

Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads
by: Kim, Jumin, et al.
Published: (2025)

Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design
by: Ye, Haojie, et al.
Published: (2024)

AMAZE: Accelerated MiMC Hardware Architecture for Zero-Knowledge Applications on the Edge
by: Ahmed, Anees, et al.
Published: (2024)

Towards Closing the Performance Gap for Cryptographic Kernels Between CPUs and Specialized Hardware
by: Zhang, Naifeng, et al.
Published: (2025)

Efficient Hardware Implementation of Modular Multiplier over GF (2m) on FPGA
by: Kumari, Ruby, et al.
Published: (2025)

An Efficient Algorithm for Modulus Operation and Its Hardware Implementation in Prime Number Calculation
by: Wijesinghe, W. A. Susantha
Published: (2024)

"vcd2df" -- Leveraging Data Science Insights for Hardware Security Research
by: Deutschbein, Calvin, et al.
Published: (2025)

Enabling Deterministic User-Level Interrupts in Real-Time Processors via Hardware Extension
by: Yang, Hongbin, et al.
Published: (2026)

ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM
by: Ku, Jonathan, et al.
Published: (2024)

An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
by: Zoni, Davide, et al.
Published: (2024)

QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL
by: Reimann, Lennart M., et al.
Published: (2024)

REDACTOR: eFPGA Redaction for DNN Accelerator Security
by: Baddour, Yazan, et al.
Published: (2025)

RTL2M$μ$PATH: Multi-$μ$PATH Synthesis with Applications to Hardware Security Verification
by: Hsiao, Yao, et al.
Published: (2024)

Hardware-Friendly Randomization: Enabling Random-Access and Minimal Wiring in FHE Accelerators with Low Total Cost
by: Rosenfeld, Ilan, et al.
Published: (2026)

SemPat: Using Hyperproperty-based Semantic Analysis to Generate Microarchitectural Attack Patterns
by: Godbole, Adwait, et al.
Published: (2024)

Attacking Delay-based PUFs with Minimal Adversary Model
by: Fei, Hongming, et al.
Published: (2024)

ROSGuard: A Bandwidth Regulation Mechanism for ROS2-based Applications
by: Puente, Jon Altonaga, et al.
Published: (2025)