Full-stack evaluation of Machine Learning inference workloads for RISC-V systems
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arXiv
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| Autores principales: | , , , , |
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| Formato: | Preprint |
| Publicado: |
2024
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| _version_ | 1866910458747813888 |
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| author | Bhattacharjee, Debjyoti Anmol Marinelli, Tommaso Pathak, Karan Kourzanov, Peter |
| author_facet | Bhattacharjee, Debjyoti Anmol Marinelli, Tommaso Pathak, Karan Kourzanov, Peter |
| contents | Architectural simulators hold a vital role in RISC-V research, providing a crucial platform for workload evaluation without the need for costly physical prototypes. They serve as a dynamic environment for exploring innovative architectural concepts, enabling swift iteration and thorough analysis of performance metrics. As deep learning algorithms become increasingly pervasive, it is essential to benchmark new architectures with machine learning workloads. The diverse computational kernels used in deep learning algorithms highlight the necessity for a comprehensive compilation toolchain to map to target hardware platforms. This study evaluates the performance of a wide array of machine learning workloads on RISC-V architectures using gem5, an open-source architectural simulator. Leveraging an open-source compilation toolchain based on Multi-Level Intermediate Representation (MLIR), the research presents benchmarking results specifically focused on deep learning inference workloads. Additionally, the study sheds light on current limitations of gem5 when simulating RISC-V architectures, offering insights for future development and refinement. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2405_15380 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Full-stack evaluation of Machine Learning inference workloads for RISC-V systems Bhattacharjee, Debjyoti Anmol Marinelli, Tommaso Pathak, Karan Kourzanov, Peter Hardware Architecture Artificial Intelligence Architectural simulators hold a vital role in RISC-V research, providing a crucial platform for workload evaluation without the need for costly physical prototypes. They serve as a dynamic environment for exploring innovative architectural concepts, enabling swift iteration and thorough analysis of performance metrics. As deep learning algorithms become increasingly pervasive, it is essential to benchmark new architectures with machine learning workloads. The diverse computational kernels used in deep learning algorithms highlight the necessity for a comprehensive compilation toolchain to map to target hardware platforms. This study evaluates the performance of a wide array of machine learning workloads on RISC-V architectures using gem5, an open-source architectural simulator. Leveraging an open-source compilation toolchain based on Multi-Level Intermediate Representation (MLIR), the research presents benchmarking results specifically focused on deep learning inference workloads. Additionally, the study sheds light on current limitations of gem5 when simulating RISC-V architectures, offering insights for future development and refinement. |
| title | Full-stack evaluation of Machine Learning inference workloads for RISC-V systems |
| topic | Hardware Architecture Artificial Intelligence |
| url | https://arxiv.org/abs/2405.15380 |