Fast ML-driven Analog Circuit Layout using Reinforcement Learning and Steiner Trees
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arXiv
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| Autores principales: | , , , |
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| Formato: | Preprint |
| Publicado: |
2024
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| Acceso en línea: | |
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| _version_ | 1866911888897474560 |
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| author | Basso, Davide Bortolussi, Luca Videnovic-Misic, Mirjana Habal, Husni |
| author_facet | Basso, Davide Bortolussi, Luca Videnovic-Misic, Mirjana Habal, Husni |
| contents | This paper presents an artificial intelligence driven methodology to reduce the bottleneck often encountered in the analog ICs layout phase. We frame the floorplanning problem as a Markov Decision Process and leverage reinforcement learning for automatic placement generation under established topological constraints. Consequently, we introduce Steiner tree-based methods for the global routing step and generate guiding paths to be used to connect every circuit block. Finally, by integrating these solutions into a procedural generation framework, we present a unified pipeline that bridges the divide between circuit design and verification steps. Experimental results demonstrate the efficacy in generating complete layouts, eventually reducing runtimes to 1.5% compared to manual efforts. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2405_16951 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Fast ML-driven Analog Circuit Layout using Reinforcement Learning and Steiner Trees Basso, Davide Bortolussi, Luca Videnovic-Misic, Mirjana Habal, Husni Machine Learning This paper presents an artificial intelligence driven methodology to reduce the bottleneck often encountered in the analog ICs layout phase. We frame the floorplanning problem as a Markov Decision Process and leverage reinforcement learning for automatic placement generation under established topological constraints. Consequently, we introduce Steiner tree-based methods for the global routing step and generate guiding paths to be used to connect every circuit block. Finally, by integrating these solutions into a procedural generation framework, we present a unified pipeline that bridges the divide between circuit design and verification steps. Experimental results demonstrate the efficacy in generating complete layouts, eventually reducing runtimes to 1.5% compared to manual efforts. |
| title | Fast ML-driven Analog Circuit Layout using Reinforcement Learning and Steiner Trees |
| topic | Machine Learning |
| url | https://arxiv.org/abs/2405.16951 |