Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification
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arXiv
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| Autores principales: | , , , |
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| Formato: | Preprint |
| Publicado: |
2024
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| _version_ | 1866909212064350208 |
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| author | Gadde, Deepak Narayan Simon, Sebastian Lettnin, Djones Ziller, Thomas |
| author_facet | Gadde, Deepak Narayan Simon, Sebastian Lettnin, Djones Ziller, Thomas |
| contents | The verification throughput is becoming a major challenge bottleneck, since the complexity and size of SoC designs are still ever increasing. Simply adding more CPU cores and running more tests in parallel will not scale anymore. This paper discusses various methods of improving verification throughput: ranking and the new machine learning (ML) based technology introduced by Cadence i.e. Xcelium ML. Both methods aim at getting comparable coverage in less CPU time by applying more efficient stimulus. Ranking selects specific seeds that simply turned out to come up with the largest coverage in previous simulations, while Xcelium ML generates optimized patterns as a result of finding correlations between randomization points and achieved coverage of previous regressions. Quantified results as well as pros & cons of each approach are discussed in this paper at the example of three actual industry projects. Both Xcelium ML and Ranking methods gave comparable compression & speedup factors around 3 consistently. But the optimized ML based regressions simulated new random scenarios occasionally producing a coverage regain of more than 100%. Finally, a methodology is proposed to use Xcelium ML efficiently throughout the product development. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2405_17481 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification Gadde, Deepak Narayan Simon, Sebastian Lettnin, Djones Ziller, Thomas Machine Learning Hardware Architecture The verification throughput is becoming a major challenge bottleneck, since the complexity and size of SoC designs are still ever increasing. Simply adding more CPU cores and running more tests in parallel will not scale anymore. This paper discusses various methods of improving verification throughput: ranking and the new machine learning (ML) based technology introduced by Cadence i.e. Xcelium ML. Both methods aim at getting comparable coverage in less CPU time by applying more efficient stimulus. Ranking selects specific seeds that simply turned out to come up with the largest coverage in previous simulations, while Xcelium ML generates optimized patterns as a result of finding correlations between randomization points and achieved coverage of previous regressions. Quantified results as well as pros & cons of each approach are discussed in this paper at the example of three actual industry projects. Both Xcelium ML and Ranking methods gave comparable compression & speedup factors around 3 consistently. But the optimized ML based regressions simulated new random scenarios occasionally producing a coverage regain of more than 100%. Finally, a methodology is proposed to use Xcelium ML efficiently throughout the product development. |
| title | Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification |
| topic | Machine Learning Hardware Architecture |
| url | https://arxiv.org/abs/2405.17481 |