Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform
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arXiv
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| Main Authors: | , , , , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866913369050578944 |
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| author | Potocnik, Viviane Colagrande, Luca Fischer, Tim Bertaccini, Luca Pagliari, Daniele Jahier Burrello, Alessio Benini, Luca |
| author_facet | Potocnik, Viviane Colagrande, Luca Fischer, Tim Bertaccini, Luca Pagliari, Daniele Jahier Burrello, Alessio Benini, Luca |
| contents | Transformer-based foundation models have become crucial for various domains, most notably natural language processing (NLP) or computer vision (CV). These models are predominantly deployed on high-performance GPUs or hardwired accelerators with highly customized, proprietary instruction sets. Until now, limited attention has been given to RISC-V-based general-purpose platforms. In our work, we present the first end-to-end inference results of transformer models on an open-source many-tiny-core RISC-V platform implementing distributed Softmax primitives and leveraging ISA extensions for SIMD floating-point operand streaming and instruction repetition, as well as specialized DMA engines to minimize costly main memory accesses and to tolerate their latency. We focus on two foundational transformer topologies, encoder-only and decoder-only models. For encoder-only models, we demonstrate a speedup of up to 12.8x between the most optimized implementation and the baseline version. We reach over 79% FPU utilization and 294 GFLOPS/W, outperforming State-of-the-Art (SoA) accelerators by more than 2x utilizing the HW platform while achieving comparable throughput per computational unit. For decoder-only topologies, we achieve 16.1x speedup in the Non-Autoregressive (NAR) mode and up to 35.6x speedup in the Autoregressive (AR) mode compared to the baseline implementation. Compared to the best SoA dedicated accelerator, we achieve 2.04x higher FPU utilization. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2405_19284 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform Potocnik, Viviane Colagrande, Luca Fischer, Tim Bertaccini, Luca Pagliari, Daniele Jahier Burrello, Alessio Benini, Luca Distributed, Parallel, and Cluster Computing Artificial Intelligence Hardware Architecture C.4; C.3; I.2 Transformer-based foundation models have become crucial for various domains, most notably natural language processing (NLP) or computer vision (CV). These models are predominantly deployed on high-performance GPUs or hardwired accelerators with highly customized, proprietary instruction sets. Until now, limited attention has been given to RISC-V-based general-purpose platforms. In our work, we present the first end-to-end inference results of transformer models on an open-source many-tiny-core RISC-V platform implementing distributed Softmax primitives and leveraging ISA extensions for SIMD floating-point operand streaming and instruction repetition, as well as specialized DMA engines to minimize costly main memory accesses and to tolerate their latency. We focus on two foundational transformer topologies, encoder-only and decoder-only models. For encoder-only models, we demonstrate a speedup of up to 12.8x between the most optimized implementation and the baseline version. We reach over 79% FPU utilization and 294 GFLOPS/W, outperforming State-of-the-Art (SoA) accelerators by more than 2x utilizing the HW platform while achieving comparable throughput per computational unit. For decoder-only topologies, we achieve 16.1x speedup in the Non-Autoregressive (NAR) mode and up to 35.6x speedup in the Autoregressive (AR) mode compared to the baseline implementation. Compared to the best SoA dedicated accelerator, we achieve 2.04x higher FPU utilization. |
| title | Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform |
| topic | Distributed, Parallel, and Cluster Computing Artificial Intelligence Hardware Architecture C.4; C.3; I.2 |
| url | https://arxiv.org/abs/2405.19284 |