:: Library Catalog

Cover Image

Saved in:

Bibliographic Details
Main Authors:	Zhou, P. J., Yu, Q., Chen, M., Wang, Y. C., Meng, L. W., Zuo, Y., Ning, N., Liu, Y., Hu, S. G., Qiao, G. C.
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture
Online Access:	https://arxiv.org/abs/2406.01151
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Neuromorphic Processor Employing FPGA Technology with Universal Interconnections
by: Harlikar, Pracheta, et al.
Published: (2025)

A 46 Gbps 12 pJ/b Sparsity-Adaptive Beamspace Equalizer for mmWave Massive MIMO in 22FDX
by: Mirfarshbafan, Seyed Hadi, et al.
Published: (2024)

ChipLight: Cross-Layer Optimization of Chiplet Design with Optical Interconnects for LLM Training
by: Bai, Kangbo, et al.
Published: (2026)

Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
by: Zhao, Hongwei, et al.
Published: (2025)

PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies
by: Iff, Patrick, et al.
Published: (2025)

Designing Reconfigurable Interconnection Network of Heterogeneous Chiplets Using Kalman Filter
by: Biglari, Siamak, et al.
Published: (2024)

A 14ns-Latency 9Gb/s 0.44mm$^2$ 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
by: Nonaca, Darja, et al.
Published: (2025)

Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
by: Barocci, Michelangelo, et al.
Published: (2026)

When Pipelined In-Memory Accelerators Meet Spiking Direct Feedback Alignment: A Co-Design for Neuromorphic Edge Computing
by: Ren, Haoxiong, et al.
Published: (2025)

DarwinWafer: A Wafer-Scale Neuromorphic Chip
by: Zhu, Xiaolei, et al.
Published: (2025)

MENAGE: Mixed-Signal Event-Driven Neuromorphic Accelerator for Edge Applications
by: Abdollahi, Armin, et al.
Published: (2024)

EA4RCA:Efficient AIE accelerator design framework for Regular Communication-Avoiding Algorithm
by: Zhang, W. B., et al.
Published: (2024)

Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures
by: Zuckerman, Joseph, et al.
Published: (2024)

Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization
by: ouyang, Yikang, et al.
Published: (2026)

COmPOSER: Circuit Optimization of mm-wave/RF circuits with Performance-Oriented Synthesis for Efficient Realizations
by: Ghosh, Subhadip, et al.
Published: (2026)

FoldedHexaTorus: An Inter-Chiplet Interconnect Topology for Chiplet-based Systems using Organic and Glass Substrates
by: Iff, Patrick, et al.
Published: (2025)

Enabling Efficient Processing of Spiking Neural Networks with On-Chip Learning on Commodity Neuromorphic Processors for Edge AI Systems
by: Putra, Rachmad Vidya Wicaksana, et al.
Published: (2025)

SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design
by: Alvanaki, Elisavet Lydia, et al.
Published: (2025)

THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures
by: Kanani, Alish, et al.
Published: (2025)

Temperature-Resilient Analog Neuromorphic Chip in Single-Polysilicon CMOS Technology
by: Rizzo, Tommaso, et al.
Published: (2024)

Rainbow: A Composable Coherence Protocol for Multi-Chip Servers
by: Menezo, Lucia G., et al.
Published: (2020)

Dynamic Tsetlin Machine Accelerators for On-Chip Training at the Edge using FPGAs
by: Mao, Gang, et al.
Published: (2025)

EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models
by: Huang, Mingqiang, et al.
Published: (2024)

When Routers, Switches and Interconnects Compute: A processing-in-interconnect Paradigm for Scalable Neuromorphic AI
by: Srivatsav, Madhuvanthi, et al.
Published: (2025)

Link Quality Aware Pathfinding for Chiplet Interconnects
by: Yen, Aaron, et al.
Published: (2026)

Governance at the Edge of Architecture: Regulating NeuroAI and Neuromorphic Systems
by: Kashif, Afifah, et al.
Published: (2026)

FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support
by: Fischer, Tim, et al.
Published: (2024)

EdgeMM: Multi-Core CPU with Heterogeneous AI-Extension and Activation-aware Weight Pruning for Multimodal LLMs at Edge
by: Bai, Kangbo, et al.
Published: (2025)

Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs
by: Wang, Xiaoke, et al.
Published: (2026)

VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification
by: Hu, Runbang, et al.
Published: (2026)

A Hybrid Delay Model for Interconnected Multi-Input Gates
by: Ferdowsi, Arman, et al.
Published: (2024)

Benchmarking the Energy Cost of Assurance in Neuromorphic Edge Robotics
by: Kaczmarek, Sylvester
Published: (2026)

Hardware-Aware DNN Compression for Homogeneous Edge Devices
by: Zhang, Kunlong, et al.
Published: (2025)

SPRING: Systematic Profiling of Randomly Interconnected Neural Networks Generated by HLS
by: Shi, Rui, et al.
Published: (2025)

NeuroVM: Dynamic Neuromorphic Hardware Virtualization
by: Isik, Murat, et al.
Published: (2024)

A Review of Memory Wall for Neuromorphic Computing
by: Le, Dexter, et al.
Published: (2025)

Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators
by: Yik, Jason, et al.
Published: (2025)

Large Processor Chip Model
by: Chang, Kaiyan, et al.
Published: (2025)

On the Impact of Intra-node Communication in the Performance of Supercomputer and Data Center Interconnection Networks
by: Tarraga-Moreno, Joaquin, et al.
Published: (2025)

A Linear-Time Algorithm for Steady-State Analysis of Electromigration in General Interconnects
by: Shohel, Mohammad Abdullah Al, et al.
Published: (2021)