Image de couverture de livre

A 0.96pJ/SOP, 30.23K-neuron/mm^2 Heterogeneous Neuromorphic Chip With Fullerene-like Interconnection Topology for Edge-AI Computing

Fuente: arXiv

Enregistré dans:

Détails bibliographiques
Auteurs principaux:	Zhou, P. J., Yu, Q., Chen, M., Wang, Y. C., Meng, L. W., Zuo, Y., Ning, N., Liu, Y., Hu, S. G., Qiao, G. C.
Format:	Preprint
Publié:	2024
Sujets:	Hardware Architecture
Accès en ligne:	Acceder al recurso
Tags:	Ajouter un tag Pas de tags, Soyez le premier à ajouter un tag!

Documents similaires

Neuromorphic Processor Employing FPGA Technology with Universal Interconnections
par: Harlikar, Pracheta, et autres
Publié: (2025)

A 46 Gbps 12 pJ/b Sparsity-Adaptive Beamspace Equalizer for mmWave Massive MIMO in 22FDX
par: Mirfarshbafan, Seyed Hadi, et autres
Publié: (2024)

ChipLight: Cross-Layer Optimization of Chiplet Design with Optical Interconnects for LLM Training
par: Bai, Kangbo, et autres
Publié: (2026)

Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
par: Zhao, Hongwei, et autres
Publié: (2025)

PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies
par: Iff, Patrick, et autres
Publié: (2025)

Designing Reconfigurable Interconnection Network of Heterogeneous Chiplets Using Kalman Filter
par: Biglari, Siamak, et autres
Publié: (2024)

A 14ns-Latency 9Gb/s 0.44mm$^2$ 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
par: Nonaca, Darja, et autres
Publié: (2025)

When Pipelined In-Memory Accelerators Meet Spiking Direct Feedback Alignment: A Co-Design for Neuromorphic Edge Computing
par: Ren, Haoxiong, et autres
Publié: (2025)

Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
par: Barocci, Michelangelo, et autres
Publié: (2026)

MENAGE: Mixed-Signal Event-Driven Neuromorphic Accelerator for Edge Applications
par: Abdollahi, Armin, et autres
Publié: (2024)

Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures
par: Zuckerman, Joseph, et autres
Publié: (2024)

DarwinWafer: A Wafer-Scale Neuromorphic Chip
par: Zhu, Xiaolei, et autres
Publié: (2025)

Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization
par: ouyang, Yikang, et autres
Publié: (2026)

EA4RCA:Efficient AIE accelerator design framework for Regular Communication-Avoiding Algorithm
par: Zhang, W. B., et autres
Publié: (2024)

FoldedHexaTorus: An Inter-Chiplet Interconnect Topology for Chiplet-based Systems using Organic and Glass Substrates
par: Iff, Patrick, et autres
Publié: (2025)

COmPOSER: Circuit Optimization of mm-wave/RF circuits with Performance-Oriented Synthesis for Efficient Realizations
par: Ghosh, Subhadip, et autres
Publié: (2026)

SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design
par: Alvanaki, Elisavet Lydia, et autres
Publié: (2025)

Rainbow: A Composable Coherence Protocol for Multi-Chip Servers
par: Menezo, Lucia G., et autres
Publié: (2020)

THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures
par: Kanani, Alish, et autres
Publié: (2025)

EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models
par: Huang, Mingqiang, et autres
Publié: (2024)

Enabling Efficient Processing of Spiking Neural Networks with On-Chip Learning on Commodity Neuromorphic Processors for Edge AI Systems
par: Putra, Rachmad Vidya Wicaksana, et autres
Publié: (2025)

Link Quality Aware Pathfinding for Chiplet Interconnects
par: Yen, Aaron, et autres
Publié: (2026)

Dynamic Tsetlin Machine Accelerators for On-Chip Training at the Edge using FPGAs
par: Mao, Gang, et autres
Publié: (2025)

Temperature-Resilient Analog Neuromorphic Chip in Single-Polysilicon CMOS Technology
par: Rizzo, Tommaso, et autres
Publié: (2024)

EdgeMM: Multi-Core CPU with Heterogeneous AI-Extension and Activation-aware Weight Pruning for Multimodal LLMs at Edge
par: Bai, Kangbo, et autres
Publié: (2025)

FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support
par: Fischer, Tim, et autres
Publié: (2024)

Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs
par: Wang, Xiaoke, et autres
Publié: (2026)

VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification
par: Hu, Runbang, et autres
Publié: (2026)

Governance at the Edge of Architecture: Regulating NeuroAI and Neuromorphic Systems
par: Kashif, Afifah, et autres
Publié: (2026)

When Routers, Switches and Interconnects Compute: A processing-in-interconnect Paradigm for Scalable Neuromorphic AI
par: Srivatsav, Madhuvanthi, et autres
Publié: (2025)

A Hybrid Delay Model for Interconnected Multi-Input Gates
par: Ferdowsi, Arman, et autres
Publié: (2024)

Hardware-Aware DNN Compression for Homogeneous Edge Devices
par: Zhang, Kunlong, et autres
Publié: (2025)

SPRING: Systematic Profiling of Randomly Interconnected Neural Networks Generated by HLS
par: Shi, Rui, et autres
Publié: (2025)

Large Processor Chip Model
par: Chang, Kaiyan, et autres
Publié: (2025)

NeuroVM: Dynamic Neuromorphic Hardware Virtualization
par: Isik, Murat, et autres
Publié: (2024)

A Review of Memory Wall for Neuromorphic Computing
par: Le, Dexter, et autres
Publié: (2025)

Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators
par: Yik, Jason, et autres
Publié: (2025)

On the Impact of Intra-node Communication in the Performance of Supercomputer and Data Center Interconnection Networks
par: Tarraga-Moreno, Joaquin, et autres
Publié: (2025)

A Linear-Time Algorithm for Steady-State Analysis of Electromigration in General Interconnects
par: Shohel, Mohammad Abdullah Al, et autres
Publié: (2021)

METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators
par: Wang, Zhao, et autres
Publié: (2021)