Integrated error-suppressed pipeline for quantum optimization of nontrivial binary combinatorial optimization problems on gate-model hardware at the 156-qubit scale

Fuente: arXiv
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Autori principali: Sachdeva, Natasha, Hartnett, Gavin S., Maity, Smarak, Marsh, Samuel, Wang, Yulun, Winick, Adam, Dougherty, Ryan, Canuto, Daniel, Chong, You Quan, Cox, G. Adam, Hush, Michael, Mundada, Pranav S., Bentley, Christopher D. B., Biercuk, Michael J., Baum, Yuval
Natura: Preprint
Pubblicazione: 2024
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author Sachdeva, Natasha
Hartnett, Gavin S.
Maity, Smarak
Marsh, Samuel
Wang, Yulun
Winick, Adam
Dougherty, Ryan
Canuto, Daniel
Chong, You Quan
Cox, G. Adam
Hush, Michael
Mundada, Pranav S.
Bentley, Christopher D. B.
Biercuk, Michael J.
Baum, Yuval
author_facet Sachdeva, Natasha
Hartnett, Gavin S.
Maity, Smarak
Marsh, Samuel
Wang, Yulun
Winick, Adam
Dougherty, Ryan
Canuto, Daniel
Chong, You Quan
Cox, G. Adam
Hush, Michael
Mundada, Pranav S.
Bentley, Christopher D. B.
Biercuk, Michael J.
Baum, Yuval
contents We introduce a novel hybrid quantum-classical variational optimization method for unconstrained binary combinatorial optimization problems on gate-model quantum computers, integrating a custom variational ansatz, staged feedback-based dual variational parameter update strategies, efficient parametric compilation, automated error suppression during hardware execution, and scalable O($n$) classical post-processing to correct for bitflip errors. Without this integrated approach, we show that standard circuit execution at scale produces output indistinguishable from random sampling, establishing the necessity of each pipeline component. We benchmark the method on IBM superconducting quantum computers for classically nontrivial optimization problems, where the optimization is conducted on hardware with no use of classical simulation or prior knowledge of the solution. For Max-Cut on random regular graphs with topologies not matched to device connectivity, the method achieves approximation ratios of 100% for unweighted 3-regular graphs up to 156 nodes, weighted regular graphs up to 80 nodes, and weighted 7-regular graphs up 50 nodes. Applied to higher-order binary optimization, the method finds the ground state energy of 127- and 156-qubit spin-glass models matched to device topology with linear, quadratic, and cubic interaction terms, achieving approximation ratios of at least 99.5% across all instances tested. The method consistently outperforms a classical local solver across all problems. Where published results on identical problem instances are available, our method demonstrates competitive or superior performance. These results demonstrate that an appropriately engineered approach enables gate-model quantum computers to produce high-quality solutions for nontrivial binary optimization problems at the 156 qubit scale, where naive implementations are insufficient for good performance.
format Preprint
id arxiv_https___arxiv_org_abs_2406_01743
institution arXiv
publishDate 2024
record_format arxiv
spellingShingle Integrated error-suppressed pipeline for quantum optimization of nontrivial binary combinatorial optimization problems on gate-model hardware at the 156-qubit scale
Sachdeva, Natasha
Hartnett, Gavin S.
Maity, Smarak
Marsh, Samuel
Wang, Yulun
Winick, Adam
Dougherty, Ryan
Canuto, Daniel
Chong, You Quan
Cox, G. Adam
Hush, Michael
Mundada, Pranav S.
Bentley, Christopher D. B.
Biercuk, Michael J.
Baum, Yuval
Quantum Physics
We introduce a novel hybrid quantum-classical variational optimization method for unconstrained binary combinatorial optimization problems on gate-model quantum computers, integrating a custom variational ansatz, staged feedback-based dual variational parameter update strategies, efficient parametric compilation, automated error suppression during hardware execution, and scalable O($n$) classical post-processing to correct for bitflip errors. Without this integrated approach, we show that standard circuit execution at scale produces output indistinguishable from random sampling, establishing the necessity of each pipeline component. We benchmark the method on IBM superconducting quantum computers for classically nontrivial optimization problems, where the optimization is conducted on hardware with no use of classical simulation or prior knowledge of the solution. For Max-Cut on random regular graphs with topologies not matched to device connectivity, the method achieves approximation ratios of 100% for unweighted 3-regular graphs up to 156 nodes, weighted regular graphs up to 80 nodes, and weighted 7-regular graphs up 50 nodes. Applied to higher-order binary optimization, the method finds the ground state energy of 127- and 156-qubit spin-glass models matched to device topology with linear, quadratic, and cubic interaction terms, achieving approximation ratios of at least 99.5% across all instances tested. The method consistently outperforms a classical local solver across all problems. Where published results on identical problem instances are available, our method demonstrates competitive or superior performance. These results demonstrate that an appropriately engineered approach enables gate-model quantum computers to produce high-quality solutions for nontrivial binary optimization problems at the 156 qubit scale, where naive implementations are insufficient for good performance.
title Integrated error-suppressed pipeline for quantum optimization of nontrivial binary combinatorial optimization problems on gate-model hardware at the 156-qubit scale
topic Quantum Physics
url https://arxiv.org/abs/2406.01743