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VerilogReader: LLM-Aided Hardware Test Generation

Fuente: arXiv

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Dettagli Bibliografici
Autori principali:	Ma, Ruiyang, Yang, Yuxin, Liu, Ziqian, Zhang, Jiaxi, Li, Min, Huang, Junhua, Luo, Guojie
Natura:	Preprint
Pubblicazione:	2024
Soggetti:	Software Engineering Artificial Intelligence
Accesso online:	Acceder al recurso
Tags:	Aggiungi Tag Nessun Tag, puoi essere il primo ad aggiungerne!!

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