A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/°C CMOS-Only Current Reference in 0.11-$μ$m Bulk and 22-nm FD-SOI
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| Formato: | Preprint |
| Publicado: |
2024
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| _version_ | 1866929588323483648 |
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| author | Lefebvre, Martin Bol, David |
| author_facet | Lefebvre, Martin Bol, David |
| contents | Internet-of-Things (IoT) applications require nW-power current references that are robust to process, voltage and temperature (PVT) variations, to maintain the performance of IoT sensor nodes in a wide range of operating conditions. However, nA-range current references are rarely area-efficient due to the use of large gate-leakage transistors or resistors, which occupy a significant silicon area at this current level. In this paper, we introduce a nA-range constant-with-temperature (CWT) current reference, relying on a self-cascode MOSFET (SCM) biased by a four-transistor ultra-low-power voltage reference through a single-transistor buffer. The proposed reference includes a temperature coefficient (TC) calibration mechanism to maintain performance across process corners. In addition, as the proposed design relies on the body effect, it has been fabricated and measured in 0.11-$μ$m bulk and 22-nm fully-depleted silicon-on-insulator (FD-SOI) to demonstrate feasibility in both technology types. On the one hand, the 0.11-$μ$m design consumes a power of 16.8 nW at 1.2 V and achieves a 2.3-nA current with a line sensitivity (LS) of 2.23 %/V at 25°C and a TC of 176 ppm/°C at 1.2 V from -40 to 85°C. On the other hand, the 22-nm design consumes a power of 16.3 nW at 1.5 V and achieves a 2.5-nA current with a 1.53-%/V LS at 25°C and an 82-ppm/°C TC at 1.5 V from -40 to 85°C. Thanks to their simple architecture, the proposed references achieve a silicon area of 0.0106 mm$^2$ in 0.11 $μ$m and 0.0026 mm$^2$ in 22 nm without compromising other figures of merit, and are thus competitive with state-of-the-art CWT references operating in the same current range. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_04741 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/°C CMOS-Only Current Reference in 0.11-$μ$m Bulk and 22-nm FD-SOI Lefebvre, Martin Bol, David Hardware Architecture B.7.0 Internet-of-Things (IoT) applications require nW-power current references that are robust to process, voltage and temperature (PVT) variations, to maintain the performance of IoT sensor nodes in a wide range of operating conditions. However, nA-range current references are rarely area-efficient due to the use of large gate-leakage transistors or resistors, which occupy a significant silicon area at this current level. In this paper, we introduce a nA-range constant-with-temperature (CWT) current reference, relying on a self-cascode MOSFET (SCM) biased by a four-transistor ultra-low-power voltage reference through a single-transistor buffer. The proposed reference includes a temperature coefficient (TC) calibration mechanism to maintain performance across process corners. In addition, as the proposed design relies on the body effect, it has been fabricated and measured in 0.11-$μ$m bulk and 22-nm fully-depleted silicon-on-insulator (FD-SOI) to demonstrate feasibility in both technology types. On the one hand, the 0.11-$μ$m design consumes a power of 16.8 nW at 1.2 V and achieves a 2.3-nA current with a line sensitivity (LS) of 2.23 %/V at 25°C and a TC of 176 ppm/°C at 1.2 V from -40 to 85°C. On the other hand, the 22-nm design consumes a power of 16.3 nW at 1.5 V and achieves a 2.5-nA current with a 1.53-%/V LS at 25°C and an 82-ppm/°C TC at 1.5 V from -40 to 85°C. Thanks to their simple architecture, the proposed references achieve a silicon area of 0.0106 mm$^2$ in 0.11 $μ$m and 0.0026 mm$^2$ in 22 nm without compromising other figures of merit, and are thus competitive with state-of-the-art CWT references operating in the same current range. |
| title | A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/°C CMOS-Only Current Reference in 0.11-$μ$m Bulk and 22-nm FD-SOI |
| topic | Hardware Architecture B.7.0 |
| url | https://arxiv.org/abs/2406.04741 |