PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs
Fuente:
arXiv
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| Main Authors: | Lou, Binglei, Rademacher, Richard, Boland, David, Leong, Philip H. W. |
|---|---|
| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | |
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