TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators
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arXiv
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| Auteurs principaux: | , , , , , |
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| Format: | Preprint |
| Publié: |
2024
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| _version_ | 1866909293287047168 |
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| author | Qin, Yifan Yan, Zheyu Pan, Zixuan Wen, Wujie Hu, Xiaobo Sharon Shi, Yiyu |
| author_facet | Qin, Yifan Yan, Zheyu Pan, Zixuan Wen, Wujie Hu, Xiaobo Sharon Shi, Yiyu |
| contents | Compute-in-memory (CIM) accelerators using non-volatile memory (NVM) devices offer promising solutions for energy-efficient and low-latency Deep Neural Network (DNN) inference execution. However, practical deployment is often hindered by the challenge of dealing with the massive amount of model weight parameters impacted by the inherent device variations within non-volatile computing-in-memory (NVCIM) accelerators. This issue significantly offsets their advantages by increasing training overhead, the time and energy needed for mapping weights to device states, and diminishing inference accuracy. To mitigate these challenges, we propose the "Tiny Shared Block (TSB)" method, which integrates a small shared 1x1 convolution block into the DNN architecture. This block is designed to stabilize feature processing across the network, effectively reducing the impact of device variation. Extensive experimental results show that TSB achieves over 20x inference accuracy gap improvement, over 5x training speedup, and weights-to-device mapping cost reduction while requiring less than 0.4% of the original weights to be write-verified during programming, when compared with state-of-the-art baseline solutions. Our approach provides a practical and efficient solution for deploying robust DNN models on NVCIM accelerators, making it a valuable contribution to the field of energy-efficient AI hardware. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_06544 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators Qin, Yifan Yan, Zheyu Pan, Zixuan Wen, Wujie Hu, Xiaobo Sharon Shi, Yiyu Hardware Architecture Artificial Intelligence Compute-in-memory (CIM) accelerators using non-volatile memory (NVM) devices offer promising solutions for energy-efficient and low-latency Deep Neural Network (DNN) inference execution. However, practical deployment is often hindered by the challenge of dealing with the massive amount of model weight parameters impacted by the inherent device variations within non-volatile computing-in-memory (NVCIM) accelerators. This issue significantly offsets their advantages by increasing training overhead, the time and energy needed for mapping weights to device states, and diminishing inference accuracy. To mitigate these challenges, we propose the "Tiny Shared Block (TSB)" method, which integrates a small shared 1x1 convolution block into the DNN architecture. This block is designed to stabilize feature processing across the network, effectively reducing the impact of device variation. Extensive experimental results show that TSB achieves over 20x inference accuracy gap improvement, over 5x training speedup, and weights-to-device mapping cost reduction while requiring less than 0.4% of the original weights to be write-verified during programming, when compared with state-of-the-art baseline solutions. Our approach provides a practical and efficient solution for deploying robust DNN models on NVCIM accelerators, making it a valuable contribution to the field of energy-efficient AI hardware. |
| title | TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators |
| topic | Hardware Architecture Artificial Intelligence |
| url | https://arxiv.org/abs/2406.06544 |