SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications
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arXiv
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| Main Authors: | , , , , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866914831130427392 |
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| author | Rogenmoser, Michael Ottaviano, Alessandro Benz, Thomas Balas, Robert Perotti, Matteo Garofalo, Angelo Benini, Luca |
| author_facet | Rogenmoser, Michael Ottaviano, Alessandro Benz, Thomas Balas, Robert Perotti, Matteo Garofalo, Angelo Benini, Luca |
| contents | In the last decade, we have witnessed exponential growth in the complexity of control systems for safety-critical applications (automotive, robots, industrial automation) and their transition to heterogeneous mixed-criticality systems (MCSs). The growth of the RISC-V ecosystem is creating a major opportunity to develop open-source, vendor-neutral reference platforms for safety-critical computing. We present SentryCore, a reliable, real-time, self-contained, open-source mega-IP for advanced control functions that can be seamlessly integrated into Systems-on-Chip, e.g., for automotive applications, through industry-standard Advanced eXtensible Interface 4 (AXI4). SentryCore features three embedded RISC-V processor cores in lockstep with error-correcting code (ECC) protected data memory for reliable execution of any safety-critical application. Context switching is accelerated to under 110 clock cycles via a RISC-V core-local interrupt controller (CLIC) and dedicated hardware extensions, while a timer-based direct memory access (DMA) engine streamlines sensor data readout during periodic control loops. SentryCore was implemented in Intel's 16nm process node and tested with FreeRTOS, ThreadX, and RTIC software support. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_06546 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications Rogenmoser, Michael Ottaviano, Alessandro Benz, Thomas Balas, Robert Perotti, Matteo Garofalo, Angelo Benini, Luca Hardware Architecture In the last decade, we have witnessed exponential growth in the complexity of control systems for safety-critical applications (automotive, robots, industrial automation) and their transition to heterogeneous mixed-criticality systems (MCSs). The growth of the RISC-V ecosystem is creating a major opportunity to develop open-source, vendor-neutral reference platforms for safety-critical computing. We present SentryCore, a reliable, real-time, self-contained, open-source mega-IP for advanced control functions that can be seamlessly integrated into Systems-on-Chip, e.g., for automotive applications, through industry-standard Advanced eXtensible Interface 4 (AXI4). SentryCore features three embedded RISC-V processor cores in lockstep with error-correcting code (ECC) protected data memory for reliable execution of any safety-critical application. Context switching is accelerated to under 110 clock cycles via a RISC-V core-local interrupt controller (CLIC) and dedicated hardware extensions, while a timer-based direct memory access (DMA) engine streamlines sensor data readout during periodic control loops. SentryCore was implemented in Intel's 16nm process node and tested with FreeRTOS, ThreadX, and RTIC software support. |
| title | SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2406.06546 |