Cover Image

Differentiable Combinatorial Scheduling at Scale

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Liu, Mingju, Li, Yingjie, Yin, Jiaqi, Zhang, Zhiru, Yu, Cunxi
Format:	Preprint
Published:	2024
Subjects:	Machine Learning Artificial Intelligence Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Differentiable Initialization-Accelerated CPU-GPU Hybrid Combinatorial Scheduling
by: Liu, Mingju, et al.
Published: (2026)

GauS: Differentiable Scheduling Optimization via Gaussian Reparameterization
by: Cai, Yaohui, et al.
Published: (2026)

MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning
by: Liu, Mingju, et al.
Published: (2024)

BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation
by: Li, Yingjie, et al.
Published: (2024)

e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving
by: Yin, Jiaqi, et al.
Published: (2025)

Revisit Choice Network for Synthesis and Technology Mapping
by: Chen, Chen, et al.
Published: (2025)

DAG-aware Synthesis Orchestration
by: Li, Yingjie, et al.
Published: (2023)

Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
by: Deng, Chenhui, et al.
Published: (2024)

Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC
by: Yu, Cunxi, et al.
Published: (2026)

Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference
by: Chen, Hongzheng, et al.
Published: (2023)

Scaling Multi-Node Mixture-of-Experts Inference Using Expert Activation Patterns
by: Bambhaniya, Abhimanyu, et al.
Published: (2026)

MixPE: Quantization and Hardware Co-design for Efficient LLM Inference
by: Zhang, Yu, et al.
Published: (2024)

FAMOUS: Flexible Accelerator for the Attention Mechanism of Transformer on UltraScale+ FPGAs
by: Kabir, Ehsan, et al.
Published: (2024)

MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models
by: Kim, Taehyun, et al.
Published: (2024)

On-Chip Hardware-Aware Quantization for Mixed Precision Neural Networks
by: Huang, Wei, et al.
Published: (2023)

InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning
by: Sun, Bin, et al.
Published: (2025)

MCU-MixQ: A HW/SW Co-optimized Mixed-precision Neural Network Design Framework for MCUs
by: Gong, Junfeng, et al.
Published: (2024)

MC$^2$A: Enabling Algorithm-Hardware Co-Design for Efficient Markov Chain Monte Carlo Acceleration
by: Zhao, Shirui, et al.
Published: (2025)

MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation
by: Zhang, Yongan, et al.
Published: (2024)

OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection
by: Cui, Fan, et al.
Published: (2024)

SmartQuant: CXL-based AI Model Store in Support of Runtime Configurable Weight Quantization
by: Xie, Rui, et al.
Published: (2024)

Tensor-Compressed and Fully-Quantized Training of Neural PDE Solvers
by: Lu, Jinming, et al.
Published: (2025)

ChipExpert: The Open-Source Integrated-Circuit-Design-Specific Large Language Model
by: Xu, Ning, et al.
Published: (2024)

LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits
by: Chang, Chen-Chia, et al.
Published: (2024)

Extending Straight-Through Estimation for Robust Neural Networks on Analog CIM Hardware
by: Feng, Yuannuo, et al.
Published: (2025)

HiFloat4 Format for Language Model Inference
by: Luo, Yuanyong, et al.
Published: (2026)

Self-Attention to Operator Learning-based 3D-IC Thermal Simulation
by: Huang, Zhen, et al.
Published: (2025)

Automated Design and Optimization of Distributed Filtering Circuits via Reinforcement Learning
by: Gao, Peng, et al.
Published: (2024)

Zero-Space Cost Fault Tolerance for Transformer-based Language Models on ReRAM
by: Li, Bingbing, et al.
Published: (2024)

AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM
by: Zhang, Yuanpeng, et al.
Published: (2025)

LUT-DLA: Lookup Table as Efficient Extreme Low-Bit Deep Learning Accelerator
by: Li, Guoyu, et al.
Published: (2025)

HPD: Hybrid Projection Decomposition for Robust State Space Models on Analog CIM Hardware
by: Feng, Yuannuo, et al.
Published: (2025)

Multimodal Chip Physical Design Engineer Assistant
by: Tsai, Yun-Da, et al.
Published: (2025)

SimPhony: A Device-Circuit-Architecture Cross-Layer Modeling and Simulation Framework for Heterogeneous Electronic-Photonic AI System
by: Yin, Ziang, et al.
Published: (2024)

AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations
by: Seo, Jamin, et al.
Published: (2025)

Report for NSF Workshop on AI for Electronic Design Automation
by: Chen, Deming, et al.
Published: (2026)

TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
by: Meng, Chang, et al.
Published: (2026)

Optimization of bi-directional gated loop cell based on multi-head attention mechanism for SSD health state classification model
by: Wen, Zhizhao, et al.
Published: (2025)

LEGO: Spatial Accelerator Generation and Optimization for Tensor Applications
by: Lin, Yujun, et al.
Published: (2025)

LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation
by: Chen, Guojin, et al.
Published: (2024)