Improving Instruction Fetch Efficiency via High-Level Program Map Traversal
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arXiv
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| Hauptverfasser: | , |
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| Format: | Preprint |
| Veröffentlicht: |
2024
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| _version_ | 1866918420855914496 |
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| author | Murthy, Shyam Sohi, Gurindar S. |
| author_facet | Murthy, Shyam Sohi, Gurindar S. |
| contents | Efficiency in instruction fetching is critical to performance, and this requires the primary structures--L1 instruction caches (L1i), branch target buffers (BTB) and instruction TLBs (iTLB)--to have the requisite information when needed. This paper proposes instruction presending, which traverses a high-level program map to identify and move instruction cache blocks, BTB entries, and iTLB entries from the secondary to the primary structures in a "just in time" fashion.
Empirical results are presented to demonstrate the efficacy of the proposed presending scheme. Presending reduces the number of cycles where the instruction fetch is waiting by an order of magnitude as compared to state-of-the-art instruction prefetching schemes while operating with small-sized primary BTBs. It is especially effective for benchmarks with a high base MPKI, where movement from secondary to primary structures is frequent. This improvement in fetch efficiency results in performance improvements in cases where this efficiency is important. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_06738 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Improving Instruction Fetch Efficiency via High-Level Program Map Traversal Murthy, Shyam Sohi, Gurindar S. Hardware Architecture Efficiency in instruction fetching is critical to performance, and this requires the primary structures--L1 instruction caches (L1i), branch target buffers (BTB) and instruction TLBs (iTLB)--to have the requisite information when needed. This paper proposes instruction presending, which traverses a high-level program map to identify and move instruction cache blocks, BTB entries, and iTLB entries from the secondary to the primary structures in a "just in time" fashion. Empirical results are presented to demonstrate the efficacy of the proposed presending scheme. Presending reduces the number of cycles where the instruction fetch is waiting by an order of magnitude as compared to state-of-the-art instruction prefetching schemes while operating with small-sized primary BTBs. It is especially effective for benchmarks with a high base MPKI, where movement from secondary to primary structures is frequent. This improvement in fetch efficiency results in performance improvements in cases where this efficiency is important. |
| title | Improving Instruction Fetch Efficiency via High-Level Program Map Traversal |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2406.06738 |