Embedded Graph Convolutional Networks for Real-Time Event Data Processing on SoC FPGAs
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arXiv
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| Format: | Preprint |
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2024
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| _version_ | 1866908430218821632 |
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| author | Jeziorek, Kamil Wzorek, Piotr Blachut, Krzysztof Pinna, Andrea Kryjak, Tomasz |
| author_facet | Jeziorek, Kamil Wzorek, Piotr Blachut, Krzysztof Pinna, Andrea Kryjak, Tomasz |
| contents | The utilisation of event cameras represents an important and swiftly evolving trend aimed at addressing the constraints of traditional video systems. Particularly within the automotive domain, these cameras find significant relevance for their integration into embedded real-time systems due to lower latency and energy consumption. One effective approach to ensure the necessary throughput and latency for event processing is through the utilisation of graph convolutional networks (GCNs). In this study, we introduce a custom EFGCN (Event-based FPGA-accelerated Graph Convolutional Network) designed with a series of hardware-aware optimisations tailored for PointNetConv, a graph convolution designed for point cloud processing. The proposed techniques result in up to 100-fold reduction in model size compared to Asynchronous Event-based GNN (AEGNN), one of the most recent works in the field, with a relatively small decrease in accuracy (2.9% for the N-Caltech101 classification task, 2.2% for the N-Cars classification task), thus following the TinyML trend. We implemented EFGCN on a ZCU104 SoC FPGA platform without any external memory resources, achieving a throughput of 13.3 million events per second (MEPS) and real-time partially asynchronous processing with low latency. Our approach achieves state-of-the-art performance across multiple event-based classification benchmarks while remaining highly scalable, customisable and resource-efficient. We publish both software and hardware source code in an open repository: https://github.com/vision-agh/gcnn-dvs-fpga |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_07318 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Embedded Graph Convolutional Networks for Real-Time Event Data Processing on SoC FPGAs Jeziorek, Kamil Wzorek, Piotr Blachut, Krzysztof Pinna, Andrea Kryjak, Tomasz Computer Vision and Pattern Recognition Hardware Architecture Image and Video Processing The utilisation of event cameras represents an important and swiftly evolving trend aimed at addressing the constraints of traditional video systems. Particularly within the automotive domain, these cameras find significant relevance for their integration into embedded real-time systems due to lower latency and energy consumption. One effective approach to ensure the necessary throughput and latency for event processing is through the utilisation of graph convolutional networks (GCNs). In this study, we introduce a custom EFGCN (Event-based FPGA-accelerated Graph Convolutional Network) designed with a series of hardware-aware optimisations tailored for PointNetConv, a graph convolution designed for point cloud processing. The proposed techniques result in up to 100-fold reduction in model size compared to Asynchronous Event-based GNN (AEGNN), one of the most recent works in the field, with a relatively small decrease in accuracy (2.9% for the N-Caltech101 classification task, 2.2% for the N-Cars classification task), thus following the TinyML trend. We implemented EFGCN on a ZCU104 SoC FPGA platform without any external memory resources, achieving a throughput of 13.3 million events per second (MEPS) and real-time partially asynchronous processing with low latency. Our approach achieves state-of-the-art performance across multiple event-based classification benchmarks while remaining highly scalable, customisable and resource-efficient. We publish both software and hardware source code in an open repository: https://github.com/vision-agh/gcnn-dvs-fpga |
| title | Embedded Graph Convolutional Networks for Real-Time Event Data Processing on SoC FPGAs |
| topic | Computer Vision and Pattern Recognition Hardware Architecture Image and Video Processing |
| url | https://arxiv.org/abs/2406.07318 |