Hardware Implementation of Soft Mapper/Demappers in Iterative EP-based Receivers
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arXiv
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| Main Authors: | , , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866916283573862400 |
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| author | Schilling, Ian Fischer Sahin, Serdar Leroux, Camille Cipriano, Antonio Maria Jego, Christophe |
| author_facet | Schilling, Ian Fischer Sahin, Serdar Leroux, Camille Cipriano, Antonio Maria Jego, Christophe |
| contents | This paper presents a comprehensive study and implementations onto FPGA device of an Expectation Propagation (EP)-based receiver for QPSK, 8-PSK, and 16-QAM. To the best of our knowledge, this is the first for this kind of receiver. The receiver implements a Frequency Domain (FD) Self-Iterated Linear Equalizer (SILE), where EP is used to approximate the true posterior distribution of the transmitted symbols with a simpler distribution. Analytical approximations for the EP feedback generation process and the three constellations are applied to lessen the complexity of the soft mapper/demapper architectures. The simulation results demonstrate that the fixed-point version performs comparably to the floating-point. Moreover, implementation results show the efficiency in terms of FPGA resource usage of the proposed architecture. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_07934 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Hardware Implementation of Soft Mapper/Demappers in Iterative EP-based Receivers Schilling, Ian Fischer Sahin, Serdar Leroux, Camille Cipriano, Antonio Maria Jego, Christophe Hardware Architecture Signal Processing This paper presents a comprehensive study and implementations onto FPGA device of an Expectation Propagation (EP)-based receiver for QPSK, 8-PSK, and 16-QAM. To the best of our knowledge, this is the first for this kind of receiver. The receiver implements a Frequency Domain (FD) Self-Iterated Linear Equalizer (SILE), where EP is used to approximate the true posterior distribution of the transmitted symbols with a simpler distribution. Analytical approximations for the EP feedback generation process and the three constellations are applied to lessen the complexity of the soft mapper/demapper architectures. The simulation results demonstrate that the fixed-point version performs comparably to the floating-point. Moreover, implementation results show the efficiency in terms of FPGA resource usage of the proposed architecture. |
| title | Hardware Implementation of Soft Mapper/Demappers in Iterative EP-based Receivers |
| topic | Hardware Architecture Signal Processing |
| url | https://arxiv.org/abs/2406.07934 |