Real-time Digital RF Emulation -- II: A Near Memory Custom Accelerator
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arXiv
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| Autori principali: | , , , , , , , , , , , , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866929384746647552 |
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| author | Mukherjee, Mandovi Mao, Xiangyu Rahman, Nael DeLude, Coleman Driscoll, Joe Sharma, Sudarshan Behnam, Payman Kamal, Uday Woo, Jongseok Kim, Daehyun Khan, Sharjeel Tong, Jianming Seo, Jamin Sinha, Prachi Swaminathan, Madhavan Krishna, Tushar Pande, Santosh Romberg, Justin Mukhopadhyay, Saibal |
| author_facet | Mukherjee, Mandovi Mao, Xiangyu Rahman, Nael DeLude, Coleman Driscoll, Joe Sharma, Sudarshan Behnam, Payman Kamal, Uday Woo, Jongseok Kim, Daehyun Khan, Sharjeel Tong, Jianming Seo, Jamin Sinha, Prachi Swaminathan, Madhavan Krishna, Tushar Pande, Santosh Romberg, Justin Mukhopadhyay, Saibal |
| contents | A near memory hardware accelerator, based on a novel direct path computational model, for real-time emulation of radio frequency systems is demonstrated. Our evaluation of hardware performance uses both application-specific integrated circuits (ASIC) and field programmable gate arrays (FPGA) methodologies: 1). The ASIC testchip implementation, using TSMC 28nm CMOS, leverages distributed autonomous control to extract concurrency in compute as well as low latency. It achieves a $518$ MHz per channel bandwidth in a prototype $4$-node system. The maximum emulation range supported in this paradigm is $9.5$ km with $0.24$ $μ$s of per-sample emulation latency. 2). The FPGA-based implementation, evaluated on a Xilinx ZCU104 board, demonstrates a $9$-node test case (two Transmitters, one Receiver, and $6$ passive reflectors) with an emulation range of $1.13$ km to $27.3$ km at $215$ MHz bandwidth. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_08714 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Real-time Digital RF Emulation -- II: A Near Memory Custom Accelerator Mukherjee, Mandovi Mao, Xiangyu Rahman, Nael DeLude, Coleman Driscoll, Joe Sharma, Sudarshan Behnam, Payman Kamal, Uday Woo, Jongseok Kim, Daehyun Khan, Sharjeel Tong, Jianming Seo, Jamin Sinha, Prachi Swaminathan, Madhavan Krishna, Tushar Pande, Santosh Romberg, Justin Mukhopadhyay, Saibal Signal Processing A near memory hardware accelerator, based on a novel direct path computational model, for real-time emulation of radio frequency systems is demonstrated. Our evaluation of hardware performance uses both application-specific integrated circuits (ASIC) and field programmable gate arrays (FPGA) methodologies: 1). The ASIC testchip implementation, using TSMC 28nm CMOS, leverages distributed autonomous control to extract concurrency in compute as well as low latency. It achieves a $518$ MHz per channel bandwidth in a prototype $4$-node system. The maximum emulation range supported in this paradigm is $9.5$ km with $0.24$ $μ$s of per-sample emulation latency. 2). The FPGA-based implementation, evaluated on a Xilinx ZCU104 board, demonstrates a $9$-node test case (two Transmitters, one Receiver, and $6$ passive reflectors) with an emulation range of $1.13$ km to $27.3$ km at $215$ MHz bandwidth. |
| title | Real-time Digital RF Emulation -- II: A Near Memory Custom Accelerator |
| topic | Signal Processing |
| url | https://arxiv.org/abs/2406.08714 |