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Python-based DSL for generating Verilog model of Synchronous Digital Circuits

Fuente: arXiv
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Bibliographic Details
Main Authors: Datar, Mandar, Hegde, Dhruva S., Prasad, Vendra Durga, Prajapati, Manish, Manikanta, Neralla, Gupta, Devansh, Pavanija, Janampalli, Pare, Pratyush, Akash, Gupta, Shivam, Patkar, Sachin B.
Format: Preprint
Published: 2024
Subjects:
Hardware Architecture
Online Access:
Acceder al recurso
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