CircuitVAE: Efficient and Scalable Latent Circuit Optimization
Fuente:
arXiv
Gespeichert in:
| Hauptverfasser: | , , , , , , |
|---|---|
| Format: | Preprint |
| Veröffentlicht: |
2024
|
| Schlagworte: | |
| Online-Zugang: | |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| _version_ | 1866917693508026368 |
|---|---|
| author | Song, Jialin Swope, Aidan Kirby, Robert Roy, Rajarshi Godil, Saad Raiman, Jonathan Catanzaro, Bryan |
| author_facet | Song, Jialin Swope, Aidan Kirby, Robert Roy, Rajarshi Godil, Saad Raiman, Jonathan Catanzaro, Bryan |
| contents | Automatically designing fast and space-efficient digital circuits is challenging because circuits are discrete, must exactly implement the desired logic, and are costly to simulate. We address these challenges with CircuitVAE, a search algorithm that embeds computation graphs in a continuous space and optimizes a learned surrogate of physical simulation by gradient descent. By carefully controlling overfitting of the simulation surrogate and ensuring diverse exploration, our algorithm is highly sample-efficient, yet gracefully scales to large problem instances and high sample budgets. We test CircuitVAE by designing binary adders across a large range of sizes, IO timing constraints, and sample budgets. Our method excels at designing large circuits, where other algorithms struggle: compared to reinforcement learning and genetic algorithms, CircuitVAE typically finds 64-bit adders which are smaller and faster using less than half the sample budget. We also find CircuitVAE can design state-of-the-art adders in a real-world chip, demonstrating that our method can outperform commercial tools in a realistic setting. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_09535 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | CircuitVAE: Efficient and Scalable Latent Circuit Optimization Song, Jialin Swope, Aidan Kirby, Robert Roy, Rajarshi Godil, Saad Raiman, Jonathan Catanzaro, Bryan Machine Learning Hardware Architecture Automatically designing fast and space-efficient digital circuits is challenging because circuits are discrete, must exactly implement the desired logic, and are costly to simulate. We address these challenges with CircuitVAE, a search algorithm that embeds computation graphs in a continuous space and optimizes a learned surrogate of physical simulation by gradient descent. By carefully controlling overfitting of the simulation surrogate and ensuring diverse exploration, our algorithm is highly sample-efficient, yet gracefully scales to large problem instances and high sample budgets. We test CircuitVAE by designing binary adders across a large range of sizes, IO timing constraints, and sample budgets. Our method excels at designing large circuits, where other algorithms struggle: compared to reinforcement learning and genetic algorithms, CircuitVAE typically finds 64-bit adders which are smaller and faster using less than half the sample budget. We also find CircuitVAE can design state-of-the-art adders in a real-world chip, demonstrating that our method can outperform commercial tools in a realistic setting. |
| title | CircuitVAE: Efficient and Scalable Latent Circuit Optimization |
| topic | Machine Learning Hardware Architecture |
| url | https://arxiv.org/abs/2406.09535 |