Cover Image

Triangel: A High-Performance, Accurate, Timely On-Chip Temporal Prefetcher

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Ainsworth, Sam, Mukhanov, Lev
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Profile-Guided Temporal Prefetching
by: Li, Mengming, et al.
Published: (2025)

Pickle Prefetcher: Programmable and Scalable Last-Level Cache Prefetcher
by: Nguyen, Hoa, et al.
Published: (2025)

Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency
by: Li, Mengming, et al.
Published: (2025)

Gaze into the Pattern: Characterizing Spatial Patterns with Internal Temporal Correlations for Hardware Prefetching
by: Chen, Zixiao, et al.
Published: (2024)

A Case for Kolmogorov-Arnold Networks in Prefetching: Towards Low-Latency, Generalizable ML-Based Prefetchers
by: Kulkarni, Dhruv, et al.
Published: (2025)

CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
by: Oh, Dongsuk, et al.
Published: (2025)

FireGuard: A Generalized Microarchitecture for Fine-Grained Security Analysis on OoO Superscalar Cores
by: Jiang, Zhe, et al.
Published: (2025)

MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors
by: Jiang, Zhe, et al.
Published: (2025)

A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering
by: Jamet, Alexandre Valentin, et al.
Published: (2024)

Exploring DRAM Cache Prefetching for Pooled Memory
by: Tirumalasetty, Chandrahas, et al.
Published: (2024)

Agile TLB Prefetching and Prediction Replacement Policy
by: Mersha, Melkamu, et al.
Published: (2024)

SPPAM: Signature Pattern Prediction and Access-Map Prefetcher
by: Merrell, Maccoy, et al.
Published: (2026)

HFRWKV: A High-Performance Fully On-Chip Hardware Accelerator for RWKV
by: Shijie, Liu, et al.
Published: (2026)

TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
by: Tozlu, Yavuz Selim, et al.
Published: (2026)

ORAP: Optimized Row Access Prefetching for Rowhammer-mitigated Memory
by: Merrell, Maccoy, et al.
Published: (2026)

ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
by: Li, Mengming, et al.
Published: (2026)

PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender
by: Li, Luyi, et al.
Published: (2023)

Towards Efficient and Accurate Detection of On-Chip Fail-Slow Failures for Many-Core Accelerators
by: Wu, Junchi, et al.
Published: (2025)

Enhancing Instruction Prefetching via Cache and TLB Management
by: Jamet, Alexandre Valentin, et al.
Published: (2026)

WaSP: Warp Scheduling to Mimic Prefetching in Graphics Workloads
by: Joseph, Diya, et al.
Published: (2024)

DEER: Deep Runahead for Instruction Prefetching on Modern Mobile Workloads
by: Vahdatniya, Parmida, et al.
Published: (2025)

A Joint Learning Approach to Hardware Caching and Prefetching
by: Yuan, Samuel, et al.
Published: (2025)

A Time- and Energy-Efficient CNN with Dense Connections on Memristor-Based Chips
by: Zhou, Wenyong, et al.
Published: (2025)

Optimizing and Exploring System Performance in Compact Processing-in-Memory-based Chips
by: Chen, Peilin, et al.
Published: (2025)

SLOFetch: Compressed-Hierarchical Instruction Prefetching for Cloud Microservices
by: Bao, Zerui, et al.
Published: (2025)

Algorithm-Driven On-Chip Integration for High Density and Low Cost
by: Kim, Jeongeun, et al.
Published: (2025)

PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching
by: Jiang, Fang, et al.
Published: (2024)

PhantomFetch: Obfuscating Loads against Prefetcher Side-Channel Attacks
by: Zhang, Xingzhi, et al.
Published: (2025)

Large Processor Chip Model
by: Chang, Kaiyan, et al.
Published: (2025)

ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
by: Yu, Zhongkai, et al.
Published: (2026)

Rainbow: A Composable Coherence Protocol for Multi-Chip Servers
by: Menezo, Lucia G., et al.
Published: (2020)

AMC: Access to Miss Correlation Prefetcher for Evolving Graph Analytics
by: Singh, Abhishek, et al.
Published: (2024)

WIP: Turning Fake Chips into Learning Opportunities
by: Mehraban, Haniye, et al.
Published: (2025)

LinkBo: An Adaptive Single-Wire, Low-Latency, and Fault-Tolerant Communications Interface for Variable-Distance Chip-to-Chip Systems
by: Ye, Bochen, et al.
Published: (2025)

Improving Chip Design Enablement for Universities in Europe -- A Position Paper
by: Krupp, Lukas, et al.
Published: (2025)

Resilient and Secure Programmable System-on-Chip Accelerator Offload
by: Gouveia, Inês Pinto, et al.
Published: (2024)

Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures
by: Zuckerman, Joseph, et al.
Published: (2024)

EONSim: An NPU Simulator for On-Chip Memory and Embedding Vector Operations
by: Choi, Sangun, et al.
Published: (2025)

Scope: A Scalable Merged Pipeline Framework for Multi-Chip-Module NN Accelerators
by: Huang, Zongle, et al.
Published: (2026)

Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
by: Zhao, Hongwei, et al.
Published: (2025)