Cover Image

Exploring DRAM Cache Prefetching for Pooled Memory

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Tirumalasetty, Chandrahas, Annapreddy, Narasimha
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Pickle Prefetcher: Programmable and Scalable Last-Level Cache Prefetcher
by: Nguyen, Hoa, et al.
Published: (2025)

Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory
by: Hong, Jeongmin, et al.
Published: (2024)

TDRAM: Tag-enhanced DRAM for Efficient Caching
by: Babaie, Maryam, et al.
Published: (2024)

Enhancing Instruction Prefetching via Cache and TLB Management
by: Jamet, Alexandre Valentin, et al.
Published: (2026)

PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender
by: Li, Luyi, et al.
Published: (2023)

ORAP: Optimized Row Access Prefetching for Rowhammer-mitigated Memory
by: Merrell, Maccoy, et al.
Published: (2026)

ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
by: Li, Mengming, et al.
Published: (2026)

A Joint Learning Approach to Hardware Caching and Prefetching
by: Yuan, Samuel, et al.
Published: (2025)

Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency
by: Li, Mengming, et al.
Published: (2025)

Shifting in-DRAM
by: Tegge, William C., et al.
Published: (2026)

PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching
by: Jiang, Fang, et al.
Published: (2024)

Profile-Guided Temporal Prefetching
by: Li, Mengming, et al.
Published: (2025)

GenDRAM:Hardware-Software Co-Design of General Platform in DRAM
by: Lu, Tsung-Han, et al.
Published: (2026)

A Case for Kolmogorov-Arnold Networks in Prefetching: Towards Low-Latency, Generalizable ML-Based Prefetchers
by: Kulkarni, Dhruv, et al.
Published: (2025)

Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture
by: Olgun, Ataberk, et al.
Published: (2022)

SoMa: Identifying, Exploring, and Understanding the DRAM Communication Scheduling Space for DNN Accelerators
by: Cai, Jingwei, et al.
Published: (2025)

Agile TLB Prefetching and Prediction Replacement Policy
by: Mersha, Melkamu, et al.
Published: (2024)

EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques
by: Canpolat, Oğuzhan, et al.
Published: (2025)

SPPAM: Signature Pattern Prediction and Access-Map Prefetcher
by: Merrell, Maccoy, et al.
Published: (2026)

FPGA-based Hyrbid Memory Emulation System
by: Wen, Fei, et al.
Published: (2020)

DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands
by: Nam, Hwayong, et al.
Published: (2024)

Kelle: Co-design KV Caching and eDRAM for Efficient LLM Serving in Edge Computing
by: Xia, Tianhua, et al.
Published: (2025)

GEM3D CIM General Purpose Matrix Computation Using 3D Integrated SRAM eDRAM Hybrid Compute In Memory on Memory Architecture
by: Chakraborty, Subhradip, et al.
Published: (2026)

ATiM: Autotuning Tensor Programs for Processing-in-DRAM
by: Shin, Yongwon, et al.
Published: (2024)

Triangel: A High-Performance, Accurate, Timely On-Chip Temporal Prefetcher
by: Ainsworth, Sam, et al.
Published: (2024)

TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
by: Tozlu, Yavuz Selim, et al.
Published: (2026)

CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
by: Oh, Dongsuk, et al.
Published: (2025)

Improving the Representativeness of Simulation Intervals for the Cache Memory System
by: Bueno, Nicolas, et al.
Published: (2024)

Hardware Memory Management for Future Mobile Hybrid Memory Systems
by: Wen, Fei, et al.
Published: (2020)

Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems
by: Patel, Minesh, et al.
Published: (2024)

Gaze into the Pattern: Characterizing Spatial Patterns with Internal Temporal Correlations for Hardware Prefetching
by: Chen, Zixiao, et al.
Published: (2024)

DRAM-Profiler: An Experimental DRAM RowHammer Vulnerability Profiling Mechanism
by: Zhou, Ranyang, et al.
Published: (2024)

CIMPool: Scalable Neural Network Acceleration for Compute-In-Memory using Weight Pools
by: Li, Shurui, et al.
Published: (2025)

CMD: A Cache-assisted GPU Memory Deduplication Architecture
by: Zhao, Wei, et al.
Published: (2024)

Corrigendum to: A Systematic Study of DDR4 DRAM Faults in the Field
by: Beigi, Majed Valad, et al.
Published: (2024)

Membrane: Accelerating Database Analytics with Bank-Level DRAM-PIM Filtering
by: Shekar, Akhil, et al.
Published: (2025)

Area-Efficient In-Memory Computing for Mixture-of-Experts via Multiplexing and Caching
by: Gao, Hanyuan, et al.
Published: (2026)

Shared-PIM: Enabling Concurrent Computation and Data Flow for Faster Processing-in-DRAM
by: Mamdouh, Ahmed, et al.
Published: (2024)

RACAM: Enhancing DRAM with Reuse-Aware Computation and Automated Mapping for ML Inference
by: Ma, Siyuan, et al.
Published: (2025)

LOCALUT: Harnessing Capacity-Computation Tradeoffs for LUT-Based Inference in DRAM-PIM
by: Hong, Junguk, et al.
Published: (2026)