RISC-V processor enhanced with a dynamic micro-decoder unit
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arXiv
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| Hauptverfasser: | , , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866911928684642304 |
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| author | Pottier, Juliette Nieddu, Thomas Gal, Bertrand Le Pillement, Sébastien Real, Maria Méndez |
| author_facet | Pottier, Juliette Nieddu, Thomas Gal, Bertrand Le Pillement, Sébastien Real, Maria Méndez |
| contents | For years, the open-source RISC-V instruction set has been driving innovation in processor design, spanning from high-end cores to low-cost or low-power cores. After a decade of evolution, RISC architectures are now as mature as the CISC architectures popularized by industry giant Intel. Security and energy efficiency are now joining execution speed among the design constraints. In this article, we assess the benefits and costs associated with integrating a micro-decoding unit inspired by CISC processors into a RISC-V core. This unit, added in a specific pipeline stage, should enable dynamic custom instruction sequences execution whose usage could be, for instance to compress binaries, obfuscate behavior, etc. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_14999 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | RISC-V processor enhanced with a dynamic micro-decoder unit Pottier, Juliette Nieddu, Thomas Gal, Bertrand Le Pillement, Sébastien Real, Maria Méndez Hardware Architecture For years, the open-source RISC-V instruction set has been driving innovation in processor design, spanning from high-end cores to low-cost or low-power cores. After a decade of evolution, RISC architectures are now as mature as the CISC architectures popularized by industry giant Intel. Security and energy efficiency are now joining execution speed among the design constraints. In this article, we assess the benefits and costs associated with integrating a micro-decoding unit inspired by CISC processors into a RISC-V core. This unit, added in a specific pipeline stage, should enable dynamic custom instruction sequences execution whose usage could be, for instance to compress binaries, obfuscate behavior, etc. |
| title | RISC-V processor enhanced with a dynamic micro-decoder unit |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2406.14999 |