Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET
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arXiv
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| Autori principali: | , , , , , , , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866909228896092160 |
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| author | Paulin, Gianna Scheffler, Paul Benz, Thomas Cavalcante, Matheus Fischer, Tim Eggimann, Manuel Zhang, Yichao Wistoff, Nils Bertaccini, Luca Colagrande, Luca Ottavi, Gianmarco Gürkaynak, Frank K. Rossi, Davide Benini, Luca |
| author_facet | Paulin, Gianna Scheffler, Paul Benz, Thomas Cavalcante, Matheus Fischer, Tim Eggimann, Manuel Zhang, Yichao Wistoff, Nils Bertaccini, Luca Colagrande, Luca Ottavi, Gianmarco Gürkaynak, Frank K. Rossi, Davide Benini, Luca |
| contents | We present Occamy, a 432-core RISC-V dual-chiplet 2.5D system for efficient sparse linear algebra and stencil computations on FP64 and narrow (32-, 16-, 8-bit) SIMD FP data. Occamy features 48 clusters of RISC-V cores with custom extensions, two 64-bit host cores, and a latency-tolerant multi-chiplet interconnect and memory system with 32 GiB of HBM2E. It achieves leading-edge utilization on stencils (83 %), sparse-dense (42 %), and sparse-sparse (49 %) matrix multiply. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_15068 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET Paulin, Gianna Scheffler, Paul Benz, Thomas Cavalcante, Matheus Fischer, Tim Eggimann, Manuel Zhang, Yichao Wistoff, Nils Bertaccini, Luca Colagrande, Luca Ottavi, Gianmarco Gürkaynak, Frank K. Rossi, Davide Benini, Luca Hardware Architecture We present Occamy, a 432-core RISC-V dual-chiplet 2.5D system for efficient sparse linear algebra and stencil computations on FP64 and narrow (32-, 16-, 8-bit) SIMD FP data. Occamy features 48 clusters of RISC-V cores with custom extensions, two 64-bit host cores, and a latency-tolerant multi-chiplet interconnect and memory system with 32 GiB of HBM2E. It achieves leading-edge utilization on stencils (83 %), sparse-dense (42 %), and sparse-sparse (49 %) matrix multiply. |
| title | Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2406.15068 |