Impact of the Top SiO2 Interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure
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arXiv
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| Autori principali: | , , , , , , , , , , , , , , , |
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| Natura: | Preprint |
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2024
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| _version_ | 1866910498557001728 |
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| author | Hu, Tao Shao, Xianzhou Bai, Mingkai Jia, Xinpei Dai, Saifei Sun, Xiaoqing Han, Runhao Yang, Jia Ke, Xiaoyu Tian, Fengbin Yang, Shuai Chai, Junshuai Xu, Hao Wang, Xiaolei Wang, Wenwu Ye, Tianchun |
| author_facet | Hu, Tao Shao, Xianzhou Bai, Mingkai Jia, Xinpei Dai, Saifei Sun, Xiaoqing Han, Runhao Yang, Jia Ke, Xiaoyu Tian, Fengbin Yang, Shuai Chai, Junshuai Xu, Hao Wang, Xiaolei Wang, Wenwu Ye, Tianchun |
| contents | We study the impact of top SiO2 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistor (FeFET) with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. We find that the MW increases with the increasing thickness of the top SiO2 interlayer, and such an increase exhibits a two-stage linear dependence. The physical origin is the presence of the different interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface. Moreover, we investigate the dependence of endurance characteristics on initial MW. We find that the endurance characteristic degrades with increasing the initial MW. By inserting a 3.4 nm SiO2 dielectric interlayer between the gate metal TiN and the ferroelectric Hf0.5Zr0.5O2, we achieve a MW of 6.3 V and retention over 10 years. Our work is helpful in the device design of FeFET. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_15478 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Impact of the Top SiO2 Interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure Hu, Tao Shao, Xianzhou Bai, Mingkai Jia, Xinpei Dai, Saifei Sun, Xiaoqing Han, Runhao Yang, Jia Ke, Xiaoyu Tian, Fengbin Yang, Shuai Chai, Junshuai Xu, Hao Wang, Xiaolei Wang, Wenwu Ye, Tianchun Materials Science Applied Physics We study the impact of top SiO2 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistor (FeFET) with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. We find that the MW increases with the increasing thickness of the top SiO2 interlayer, and such an increase exhibits a two-stage linear dependence. The physical origin is the presence of the different interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface. Moreover, we investigate the dependence of endurance characteristics on initial MW. We find that the endurance characteristic degrades with increasing the initial MW. By inserting a 3.4 nm SiO2 dielectric interlayer between the gate metal TiN and the ferroelectric Hf0.5Zr0.5O2, we achieve a MW of 6.3 V and retention over 10 years. Our work is helpful in the device design of FeFET. |
| title | Impact of the Top SiO2 Interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure |
| topic | Materials Science Applied Physics |
| url | https://arxiv.org/abs/2406.15478 |