LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
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| Main Authors: | , , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866908415288147968 |
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| author | Bhandari, Jitendra Knechtel, Johann Narayanaswamy, Ramesh Garg, Siddharth Karri, Ramesh |
| author_facet | Bhandari, Jitendra Knechtel, Johann Narayanaswamy, Ramesh Garg, Siddharth Karri, Ramesh |
| contents | This work investigates the potential of tailoring Large Language Models (LLMs), specifically GPT3.5 and GPT4, for the domain of chip testing. A key aspect of chip design is functional testing, which relies on testbenches to evaluate the functionality and coverage of Register-Transfer Level (RTL) designs. We aim to enhance testbench generation by incorporating feedback from commercial-grade Electronic Design Automation (EDA) tools into LLMs. Through iterative feedback from these tools, we refine the testbenches to achieve improved test coverage. Our case studies present promising results, demonstrating that this approach can effectively enhance test coverage. By integrating EDA tool feedback, the generated testbenches become more accurate in identifying potential issues in the RTL design. Furthermore, we extended our study to use this enhanced test coverage framework for detecting bugs in the RTL implementations |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_17132 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines Bhandari, Jitendra Knechtel, Johann Narayanaswamy, Ramesh Garg, Siddharth Karri, Ramesh Hardware Architecture This work investigates the potential of tailoring Large Language Models (LLMs), specifically GPT3.5 and GPT4, for the domain of chip testing. A key aspect of chip design is functional testing, which relies on testbenches to evaluate the functionality and coverage of Register-Transfer Level (RTL) designs. We aim to enhance testbench generation by incorporating feedback from commercial-grade Electronic Design Automation (EDA) tools into LLMs. Through iterative feedback from these tools, we refine the testbenches to achieve improved test coverage. Our case studies present promising results, demonstrating that this approach can effectively enhance test coverage. By integrating EDA tool feedback, the generated testbenches become more accurate in identifying potential issues in the RTL design. Furthermore, we extended our study to use this enhanced test coverage framework for detecting bugs in the RTL implementations |
| title | LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2406.17132 |