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Hypervisor Extension for a RISC-V Processor

Fuente: arXiv

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Bibliographic Details
Main Authors:	Gauchola, Jaume, Costa, JuanJosé, Morancho, Enric, Canal, Ramon, Carril, Xavier, Doblas, Max, Otero, Beatriz, Pajuelo, Alex, Rodríguez, Eva, Salamero, Javier, Verdú, Javier
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
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_version_	1866911933313056768
author	Gauchola, Jaume Costa, JuanJosé Morancho, Enric Canal, Ramon Carril, Xavier Doblas, Max Otero, Beatriz Pajuelo, Alex Rodríguez, Eva Salamero, Javier Verdú, Javier
author_facet	Gauchola, Jaume Costa, JuanJosé Morancho, Enric Canal, Ramon Carril, Xavier Doblas, Max Otero, Beatriz Pajuelo, Alex Rodríguez, Eva Salamero, Javier Verdú, Javier
contents	This paper describes our experience implementing a Hypervisor extension for a 64-bit RISC-V processor. We describe the design process and the main required parts with a brief explanation of each one.
format	Preprint
id	arxiv_https___arxiv_org_abs_2406_17796
institution	arXiv
publishDate	2024
record_format	arxiv
spellingShingle	Hypervisor Extension for a RISC-V Processor Gauchola, Jaume Costa, JuanJosé Morancho, Enric Canal, Ramon Carril, Xavier Doblas, Max Otero, Beatriz Pajuelo, Alex Rodríguez, Eva Salamero, Javier Verdú, Javier Hardware Architecture This paper describes our experience implementing a Hypervisor extension for a 64-bit RISC-V processor. We describe the design process and the main required parts with a brief explanation of each one.
title	Hypervisor Extension for a RISC-V Processor
topic	Hardware Architecture
url	https://arxiv.org/abs/2406.17796