Cover Image

High-Resolution, Multi-Channel FPGA-Based Time-to-Digital Converter

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Jakli, Balazs, Rak, Adam, Cserey, Gyorgy
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

A Security-Aware Nonlinearity Study of FPGA-Based Time-to-Digital Converters for Quantum Key Distribution Systems
by: Qin, Kun, et al.
Published: (2026)

Delay Time Characterization on FPGA: A Low Nonlinearity, Picosecond Resolution Time-to-Digital Converter on 16-nm FPGA using Bin Sequence Calibration
by: Park, Sunwoo, et al.
Published: (2025)

Binary Neural Network Implementation for Handwritten Digit Recognition on FPGA
by: Ertörer, Emir Devlet, et al.
Published: (2025)

Real Time FPGA Based Transformers & VLMs for Vision Tasks: SOTA Designs and Optimizations
by: Sali, Safa Mohammed, et al.
Published: (2025)

Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms
by: Galimberti, Andrea, et al.
Published: (2024)

Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design
by: Andrulis, Tanner, et al.
Published: (2024)

FPPS: An FPGA-Based Point Cloud Processing System
by: Zhou, Xiaofeng, et al.
Published: (2026)

Design and Implementation of BNN-Based Object Detection on FPGA
by: Zhao, Xuyu, et al.
Published: (2026)

TerEffic: Highly Efficient Ternary LLM Inference on FPGA
by: Yin, Chenyang, et al.
Published: (2025)

Real Time FPGA Based CNNs for Detection, Classification, and Tracking in Autonomous Systems: State of the Art Designs and Optimizations
by: Sali, Safa Mohammed, et al.
Published: (2025)

A High-Throughput FPGA Accelerator for Lightweight CNNs With Balanced Dataflow
by: Zhao, Zhiyuan, et al.
Published: (2024)

An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
by: Zoni, Davide, et al.
Published: (2024)

Real-Time, Energy-Efficient, Sampling-Based Optimal Control via FPGA Acceleration
by: Desai, Tanmay, et al.
Published: (2026)

Swift: A Multi-FPGA Framework for Scaling Up Accelerated Graph Analytics
by: Jaiyeoba, Oluwole, et al.
Published: (2024)

Facial Expression Recognition System Using DNN Accelerator with Multi-threading on FPGA
by: Ando, Takuto, et al.
Published: (2025)

SuperUROP: An FPGA-Based Spatial Accelerator for Sparse Matrix Operations
by: Parthasarathy, Rishab
Published: (2025)

Design of a 6-bit Threshold Inverter Quantization (TIQ) Flash Analog to Digital Converter (ADC)
by: Sarkar, Noyon Kumar, et al.
Published: (2025)

RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System
by: Fu, Zizhuo, et al.
Published: (2026)

Revealing Untapped DSP Optimization Potentials for FPGA-Based Systolic Matrix Engines
by: Li, Jindong, et al.
Published: (2024)

A Scalable FPGA Architecture With Adaptive Memory Utilization for GEMM-Based Operations
by: Petropoulos, Anastasios, et al.
Published: (2025)

Real-Time Adaptive Neural Network on FPGA: Enhancing Adaptability through Dynamic Classifier Selection
by: Bouazzaoui, Achraf El, et al.
Published: (2023)

Holistic Optimization Framework for FPGA Accelerators
by: Pouget, Stéphane, et al.
Published: (2025)

RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs
by: Kim, Jiho, et al.
Published: (2025)

LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization
by: Di, Zhixiong, et al.
Published: (2023)

Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators
by: Masar, Filip, et al.
Published: (2025)

FPGA-Based Multiplier with a New Approximate Full Adder for Error-Resilient Applications
by: Ranjbar, Ali, et al.
Published: (2025)

EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models
by: Huang, Mingqiang, et al.
Published: (2024)

Development of High-Performance DSP Algorithms on the European Rad-Hard NG-ULTRA SoC FPGA
by: Leon, Vasileios, et al.
Published: (2024)

A Hybrid Residue Floating Numerical Architecture with Formal Error Bounds for High Throughput FPGA Computation
by: Darvishi, Mostafa
Published: (2026)

FastFlow in FPGA Stacks of Data Centers
by: Paul, Rourab, et al.
Published: (2024)

Demystifying FPGA Hard NoC Performance
by: Liu, Sihao, et al.
Published: (2025)

FPGA-based Hyrbid Memory Emulation System
by: Wen, Fei, et al.
Published: (2020)

Efficient and Accurate Graph Classification with Hyperdimensional Computing on FPGA
by: Arockiaraj, Jebacyril, et al.
Published: (2025)

LUTstructions: Self-loading FPGA-based Reconfigurable Instructions
by: Papaphilippou, Philippos
Published: (2026)

Bombyx: OpenCilk Compilation for FPGA Hardware Acceleration
by: Shahawy, Mohamed, et al.
Published: (2025)

Implementation and Analysis of Thermometer Encoding in DWN FPGA Accelerators
by: Mecik, Michael, et al.
Published: (2025)

An FPGA Compiler for On-the-Fly Adaptive CNN Deployment and Reconfiguration
by: Mazouz, Alaa, et al.
Published: (2025)

Neuromorphic Processor Employing FPGA Technology with Universal Interconnections
by: Harlikar, Pracheta, et al.
Published: (2025)

EMiX: Emulating Beyond Single-FPGA Limits
by: Kropotov, Alexander, et al.
Published: (2026)

Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper
by: Yu, Cunxi
Published: (2025)