Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor
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arXiv
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| Autores principales: | , , , , |
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| Formato: | Preprint |
| Publicado: |
2024
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| _version_ | 1866916301384974336 |
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| author | Papadopoulos, Nikolaos-Charalampos Psomadakis, Stratos Karakostas, Vasileios Koziris, Nectarios Pnevmatikatos, Dionisios N. |
| author_facet | Papadopoulos, Nikolaos-Charalampos Psomadakis, Stratos Karakostas, Vasileios Koziris, Nectarios Pnevmatikatos, Dionisios N. |
| contents | The RISC-V SVNAPOT Extension aims to remedy the performance overhead of the Memory Management Unit (MMU), under heavy memory loads. The Privileged Specification defines additional Natural-Power-of-Two (NAPOT) multiples of the 4KB base page size, with 64KB as the default candidate. In this paper we extend the MMU of the Rocket Chip Generator, in order to manage the collocation of 64KB pages along with 4KB pages in the L2 TLB. We present the design challenges we had to overcome and the trade-offs of our design choices. We conduct a preliminary sensitivity analysis of the L2 TLB with different configurations/page sizes. Finally, we summarize on techniques which could further improve memory management performance on RISC-V systems. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_17802 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor Papadopoulos, Nikolaos-Charalampos Psomadakis, Stratos Karakostas, Vasileios Koziris, Nectarios Pnevmatikatos, Dionisios N. Hardware Architecture The RISC-V SVNAPOT Extension aims to remedy the performance overhead of the Memory Management Unit (MMU), under heavy memory loads. The Privileged Specification defines additional Natural-Power-of-Two (NAPOT) multiples of the 4KB base page size, with 64KB as the default candidate. In this paper we extend the MMU of the Rocket Chip Generator, in order to manage the collocation of 64KB pages along with 4KB pages in the L2 TLB. We present the design challenges we had to overcome and the trade-offs of our design choices. We conduct a preliminary sensitivity analysis of the L2 TLB with different configurations/page sizes. Finally, we summarize on techniques which could further improve memory management performance on RISC-V systems. |
| title | Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2406.17802 |