Managing Classical Processing Requirements for Quantum Error Correction
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arXiv
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| Main Authors: | , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866910226686410752 |
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| author | Maurya, Satvik Molavi, Abtin Albarghouthi, Aws Tannu, Swamit |
| author_facet | Maurya, Satvik Molavi, Abtin Albarghouthi, Aws Tannu, Swamit |
| contents | Large-scale quantum computers promise transformative speedups, but their viability hinges on fast and reliable quantum error correction (QEC). At the center of QEC are decoders-classical algorithms running on hardware such as FPGAs, GPUs, or CPUs that process error syndromes to detect errors every microsecond to preserve fault-tolerance. Quantum processors, therefore, operate not in isolation, but as accelerators tightly coupled with powerful classical digital hardware. A key challenge is that decoder demand fluctuates unpredictably: bursts of activity can require orders of magnitude more decodes than idle periods. Provisioning hardware for the worst case wastes resources, while provisioning for the average case risks catastrophic slowdowns. We show that this mismatch is a systems problem of capacity planning and scheduling, and propose a two-level framework that treats decoders as shared accelerators managed by the quantum operating system. Our approach reduces decoder requirements by 10-40% across fault-tolerant benchmarks, demonstrating that efficient decoder scheduling is essential to making FTQC practical. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_17995 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Managing Classical Processing Requirements for Quantum Error Correction Maurya, Satvik Molavi, Abtin Albarghouthi, Aws Tannu, Swamit Quantum Physics Hardware Architecture Large-scale quantum computers promise transformative speedups, but their viability hinges on fast and reliable quantum error correction (QEC). At the center of QEC are decoders-classical algorithms running on hardware such as FPGAs, GPUs, or CPUs that process error syndromes to detect errors every microsecond to preserve fault-tolerance. Quantum processors, therefore, operate not in isolation, but as accelerators tightly coupled with powerful classical digital hardware. A key challenge is that decoder demand fluctuates unpredictably: bursts of activity can require orders of magnitude more decodes than idle periods. Provisioning hardware for the worst case wastes resources, while provisioning for the average case risks catastrophic slowdowns. We show that this mismatch is a systems problem of capacity planning and scheduling, and propose a two-level framework that treats decoders as shared accelerators managed by the quantum operating system. Our approach reduces decoder requirements by 10-40% across fault-tolerant benchmarks, demonstrating that efficient decoder scheduling is essential to making FTQC practical. |
| title | Managing Classical Processing Requirements for Quantum Error Correction |
| topic | Quantum Physics Hardware Architecture |
| url | https://arxiv.org/abs/2406.17995 |