Resilient and Secure Programmable System-on-Chip Accelerator Offload
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arXiv
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| Autori principali: | , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866910502414712832 |
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| author | Gouveia, Inês Pinto Sheikh, Ahmad T. Shoker, Ali Fahmy, Suhaib A. Esteves-Verissimo, Paulo |
| author_facet | Gouveia, Inês Pinto Sheikh, Ahmad T. Shoker, Ali Fahmy, Suhaib A. Esteves-Verissimo, Paulo |
| contents | Computational offload to hardware accelerators is gaining traction due to increasing computational demands and efficiency challenges. Programmable hardware, like FPGAs, offers a promising platform in rapidly evolving application areas, with the benefits of hardware acceleration and software programmability. Unfortunately, such systems composed of multiple hardware components must consider integrity in the case of malicious components. In this work, we propose Samsara, the first secure and resilient platform that derives, from Byzantine Fault Tolerant (BFT), protocols to enhance the computing resilience of programmable hardware. Samsara uses a novel lightweight hardware-based BFT protocol for Systems-on-Chip, called H-Quorum, that implements the theoretical-minimum latency between applications and replicated compute nodes. To withstand malicious behaviors, Samsara supports hardware rejuvenation, which is used to replace, relocate, or diversify faulty compute nodes. Samsara's architecture ensures the security of the entire workflow while keeping the latency overhead, of both computation and rejuvenation, close to the non-replicated counterpart. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_18117 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Resilient and Secure Programmable System-on-Chip Accelerator Offload Gouveia, Inês Pinto Sheikh, Ahmad T. Shoker, Ali Fahmy, Suhaib A. Esteves-Verissimo, Paulo Hardware Architecture Computational offload to hardware accelerators is gaining traction due to increasing computational demands and efficiency challenges. Programmable hardware, like FPGAs, offers a promising platform in rapidly evolving application areas, with the benefits of hardware acceleration and software programmability. Unfortunately, such systems composed of multiple hardware components must consider integrity in the case of malicious components. In this work, we propose Samsara, the first secure and resilient platform that derives, from Byzantine Fault Tolerant (BFT), protocols to enhance the computing resilience of programmable hardware. Samsara uses a novel lightweight hardware-based BFT protocol for Systems-on-Chip, called H-Quorum, that implements the theoretical-minimum latency between applications and replicated compute nodes. To withstand malicious behaviors, Samsara supports hardware rejuvenation, which is used to replace, relocate, or diversify faulty compute nodes. Samsara's architecture ensures the security of the entire workflow while keeping the latency overhead, of both computation and rejuvenation, close to the non-replicated counterpart. |
| title | Resilient and Secure Programmable System-on-Chip Accelerator Offload |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2406.18117 |