Designing Unit Ising Models for Logic Gate Simulation through Integer Linear Programming
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866910502434635776 |
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| author | Tsukiyama, Shunsuke Nakano, Koji Li, Xiaotian Ito, Yasuaki Kato, Takumi Kawamata, Yuya |
| author_facet | Tsukiyama, Shunsuke Nakano, Koji Li, Xiaotian Ito, Yasuaki Kato, Takumi Kawamata, Yuya |
| contents | An Ising model is defined by a quadratic objective function known as the Hamiltonian, composed of spin variables that can take values of either $-1$ or $+1$. The goal is to assign spin values to these variables in a way that minimizes the value of the Hamiltonian. Ising models are instrumental in tackling many combinatorial optimization problems, leading to significant research in developing solvers for them. Notably, D-Wave Systems has pioneered the creation of quantum annealers, programmable solvers based on quantum mechanics, for these models. This paper introduces unit Ising models, where all non-zero coefficients of linear and quadratic terms are either $-1$ or $+1$. Due to the limited resolution of quantum annealers, unit Ising models are more suitable for quantum annealers to find optimal solutions. We propose a novel design methodology for unit Ising models to simulate logic circuits computing Boolean functions through integer linear programming. By optimizing these Ising models with quantum annealers, we can compute Boolean functions and their inverses. With a fixed unit Ising model for a logic circuit, we can potentially design Application-Specific Unit Quantum Annealers (ASUQAs) for computing the inverse function, which is analogous to Application-Specific Integrated Circuits (ASICs) in digital circuitry. For instance, if we apply this technique to a multiplication circuit, we can design an ASUQA for factorization of two numbers. Our findings suggest a powerful new method for compromising the RSA cryptosystem by leveraging ASUQAs in factorization. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_18130 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Designing Unit Ising Models for Logic Gate Simulation through Integer Linear Programming Tsukiyama, Shunsuke Nakano, Koji Li, Xiaotian Ito, Yasuaki Kato, Takumi Kawamata, Yuya Emerging Technologies An Ising model is defined by a quadratic objective function known as the Hamiltonian, composed of spin variables that can take values of either $-1$ or $+1$. The goal is to assign spin values to these variables in a way that minimizes the value of the Hamiltonian. Ising models are instrumental in tackling many combinatorial optimization problems, leading to significant research in developing solvers for them. Notably, D-Wave Systems has pioneered the creation of quantum annealers, programmable solvers based on quantum mechanics, for these models. This paper introduces unit Ising models, where all non-zero coefficients of linear and quadratic terms are either $-1$ or $+1$. Due to the limited resolution of quantum annealers, unit Ising models are more suitable for quantum annealers to find optimal solutions. We propose a novel design methodology for unit Ising models to simulate logic circuits computing Boolean functions through integer linear programming. By optimizing these Ising models with quantum annealers, we can compute Boolean functions and their inverses. With a fixed unit Ising model for a logic circuit, we can potentially design Application-Specific Unit Quantum Annealers (ASUQAs) for computing the inverse function, which is analogous to Application-Specific Integrated Circuits (ASICs) in digital circuitry. For instance, if we apply this technique to a multiplication circuit, we can design an ASUQA for factorization of two numbers. Our findings suggest a powerful new method for compromising the RSA cryptosystem by leveraging ASUQAs in factorization. |
| title | Designing Unit Ising Models for Logic Gate Simulation through Integer Linear Programming |
| topic | Emerging Technologies |
| url | https://arxiv.org/abs/2406.18130 |