SubLock: Sub-Circuit Replacement based Input Dependent Key-based Logic Locking for Robust IP Protection
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arXiv
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| Auteurs principaux: | , , , |
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| Format: | Preprint |
| Publié: |
2024
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| _version_ | 1866910504250769408 |
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| author | Rathor, Vijaypal Singh Singh, Munesh Sahoo, Kshira Sagar Mohanty, Saraju P. |
| author_facet | Rathor, Vijaypal Singh Singh, Munesh Sahoo, Kshira Sagar Mohanty, Saraju P. |
| contents | Intellectual Property (IP) piracy, overbuilding, reverse engineering, and hardware Trojan are serious security concerns during integrated circuit (IC) development. Logic locking has proven to be a solid defence for mitigating these threats. The existing logic locking techniques are vulnerable to SAT-based attacks. However, several SAT-resistant logic locking methods are reported; they require significant overhead. This paper proposes a novel input dependent key-based logic locking (IDKLL) that effectively prevents SAT-based attacks with low overhead. We first introduce a novel idea of IDKLL, where a design is locked such that it functions correctly for all input patterns only when their corresponding valid key sequences are applied. In contrast to conventional logic locking, the proposed IDKLL method uses multiple key sequences (instead of a single key sequence) as a valid key that provides correct functionality for all inputs. Further, we propose a sub-circuit replacement based IDKLL approach called SubLock that locks the design by replacing the original sub-circuitry with the corresponding IDKLL based locked circuit to prevent SAT attack with low overhead. The experimental evaluation on ISCAS benchmarks shows that the proposed SubLock mitigates the SAT attack with high security and reduced overhead over the well-known existing methods. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2406_19091 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | SubLock: Sub-Circuit Replacement based Input Dependent Key-based Logic Locking for Robust IP Protection Rathor, Vijaypal Singh Singh, Munesh Sahoo, Kshira Sagar Mohanty, Saraju P. Cryptography and Security Intellectual Property (IP) piracy, overbuilding, reverse engineering, and hardware Trojan are serious security concerns during integrated circuit (IC) development. Logic locking has proven to be a solid defence for mitigating these threats. The existing logic locking techniques are vulnerable to SAT-based attacks. However, several SAT-resistant logic locking methods are reported; they require significant overhead. This paper proposes a novel input dependent key-based logic locking (IDKLL) that effectively prevents SAT-based attacks with low overhead. We first introduce a novel idea of IDKLL, where a design is locked such that it functions correctly for all input patterns only when their corresponding valid key sequences are applied. In contrast to conventional logic locking, the proposed IDKLL method uses multiple key sequences (instead of a single key sequence) as a valid key that provides correct functionality for all inputs. Further, we propose a sub-circuit replacement based IDKLL approach called SubLock that locks the design by replacing the original sub-circuitry with the corresponding IDKLL based locked circuit to prevent SAT attack with low overhead. The experimental evaluation on ISCAS benchmarks shows that the proposed SubLock mitigates the SAT attack with high security and reduced overhead over the well-known existing methods. |
| title | SubLock: Sub-Circuit Replacement based Input Dependent Key-based Logic Locking for Robust IP Protection |
| topic | Cryptography and Security |
| url | https://arxiv.org/abs/2406.19091 |