An Open-Source Fast Parallel Routing Approach for Commercial FPGAs
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arXiv
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| Main Authors: | , , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866914854050201600 |
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| author | Zang, Xinshi Lin, Wenhao Lin, Shiju Liu, Jinwei Young, Evangeline F. Y. |
| author_facet | Zang, Xinshi Lin, Wenhao Lin, Shiju Liu, Jinwei Young, Evangeline F. Y. |
| contents | In the face of escalating complexity and size of contemporary FPGAs and circuits, routing emerges as a pivotal and time-intensive phase in FPGA compilation flows. In response to this challenge, we present an open-source parallel routing methodology designed to expedite routing procedures for commercial FPGAs. Our approach introduces a novel recursive partitioning ternary tree to augment the parallelism of multi-net routing. Additionally, we propose a hybrid updating strategy for congestion coefficients within the routing cost function to accelerate congestion resolution in negotiation-based routing algorithms. Evaluation on public benchmarks from the FPGA24 routing contest demonstrates the efficacy of our parallel router. It achieves a 2x speedup compared to the academic serial router RWRoute. Furthermore, when compared to the industry-standard tool Vivado, our approach not only delivers a 2x acceleration but also yields a notable 31% enhancement in critical-path wirelength. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2407_00009 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | An Open-Source Fast Parallel Routing Approach for Commercial FPGAs Zang, Xinshi Lin, Wenhao Lin, Shiju Liu, Jinwei Young, Evangeline F. Y. Distributed, Parallel, and Cluster Computing Networking and Internet Architecture In the face of escalating complexity and size of contemporary FPGAs and circuits, routing emerges as a pivotal and time-intensive phase in FPGA compilation flows. In response to this challenge, we present an open-source parallel routing methodology designed to expedite routing procedures for commercial FPGAs. Our approach introduces a novel recursive partitioning ternary tree to augment the parallelism of multi-net routing. Additionally, we propose a hybrid updating strategy for congestion coefficients within the routing cost function to accelerate congestion resolution in negotiation-based routing algorithms. Evaluation on public benchmarks from the FPGA24 routing contest demonstrates the efficacy of our parallel router. It achieves a 2x speedup compared to the academic serial router RWRoute. Furthermore, when compared to the industry-standard tool Vivado, our approach not only delivers a 2x acceleration but also yields a notable 31% enhancement in critical-path wirelength. |
| title | An Open-Source Fast Parallel Routing Approach for Commercial FPGAs |
| topic | Distributed, Parallel, and Cluster Computing Networking and Internet Architecture |
| url | https://arxiv.org/abs/2407.00009 |