Multi-Objective Optimization for Common-Centroid Placement of Analog Transistors

Fuente: arXiv
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Hauptverfasser: Maji, Supriyo, Park, Hyungjoo, Hong, Gi moon, Poddar, Souradip, Pan, David Z.
Format: Preprint
Veröffentlicht: 2024
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author Maji, Supriyo
Park, Hyungjoo
Hong, Gi moon
Poddar, Souradip
Pan, David Z.
author_facet Maji, Supriyo
Park, Hyungjoo
Hong, Gi moon
Poddar, Souradip
Pan, David Z.
contents In analog circuits, process variation can cause unpredictability in circuit performance. Common-centroid (CC) type layouts have been shown to mitigate process-induced variations and are widely used to match circuit elements. Nevertheless, selecting the most suitable CC topology necessitates careful consideration of important layout constraints. Manual handling of these constraints becomes challenging, especially with large size problems. State-of-the-art CC placement methods lack an optimization framework to handle important layout constraints collectively. They also require manual efforts and consequently, the solutions can be suboptimal. To address this, we propose a unified framework based on multi-objective optimization for CC placement of analog transistors. Our method handles various constraints, including degree of dispersion, routing complexity, diffusion sharing, and layout dependent effects. The multi-objective optimization provides better handling of the objectives when compared to single-objective optimization. Moreover, compared to existing methods, our method explores more CC topologies. Post-layout simulation results show better performance compared to state-of-the-art techniques in generating CC layouts.
format Preprint
id arxiv_https___arxiv_org_abs_2407_00817
institution arXiv
publishDate 2024
record_format arxiv
spellingShingle Multi-Objective Optimization for Common-Centroid Placement of Analog Transistors
Maji, Supriyo
Park, Hyungjoo
Hong, Gi moon
Poddar, Souradip
Pan, David Z.
Hardware Architecture
In analog circuits, process variation can cause unpredictability in circuit performance. Common-centroid (CC) type layouts have been shown to mitigate process-induced variations and are widely used to match circuit elements. Nevertheless, selecting the most suitable CC topology necessitates careful consideration of important layout constraints. Manual handling of these constraints becomes challenging, especially with large size problems. State-of-the-art CC placement methods lack an optimization framework to handle important layout constraints collectively. They also require manual efforts and consequently, the solutions can be suboptimal. To address this, we propose a unified framework based on multi-objective optimization for CC placement of analog transistors. Our method handles various constraints, including degree of dispersion, routing complexity, diffusion sharing, and layout dependent effects. The multi-objective optimization provides better handling of the objectives when compared to single-objective optimization. Moreover, compared to existing methods, our method explores more CC topologies. Post-layout simulation results show better performance compared to state-of-the-art techniques in generating CC layouts.
title Multi-Objective Optimization for Common-Centroid Placement of Analog Transistors
topic Hardware Architecture
url https://arxiv.org/abs/2407.00817