Copertina

MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation

Fuente: arXiv

Salvato in:

Dettagli Bibliografici
Autori principali:	Zhang, Yongan, Yu, Zhongzhi, Fu, Yonggan, Wan, Cheng, Lin, Yingyan Celine
Natura:	Preprint
Pubblicazione:	2024
Soggetti:	Machine Learning Artificial Intelligence Hardware Architecture
Accesso online:	Acceder al recurso
Tags:	Aggiungi Tag Nessun Tag, puoi essere il primo ad aggiungerne!!

Documenti analoghi

GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models
di: Fu, Yonggan, et al.
Pubblicazione: (2023)

hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation
di: Hong, Charles, et al.
Pubblicazione: (2025)

VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation
di: Calzada, Paul E., et al.
Pubblicazione: (2025)

EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code
di: Guo, Ping, et al.
Pubblicazione: (2025)

HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design
di: Tang, Jinwei, et al.
Pubblicazione: (2024)

PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
di: Nadimi, Bardia, et al.
Pubblicazione: (2024)

AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs
di: Gao, Mingzhe, et al.
Pubblicazione: (2024)

VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation
di: Wang, Yiting, et al.
Pubblicazione: (2025)

Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
di: Wang, Ning, et al.
Pubblicazione: (2025)

VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
di: Nadimi, Bardia, et al.
Pubblicazione: (2025)

Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
di: Yang, Guang, et al.
Pubblicazione: (2025)

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols
di: Sheth, Arnav, et al.
Pubblicazione: (2025)

ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model
di: Qin, Haiyan, et al.
Pubblicazione: (2025)

Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
di: Wang, Ning, et al.
Pubblicazione: (2024)

VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts
di: Zhao, Jiayu, et al.
Pubblicazione: (2025)

Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
di: Blocklove, Jason, et al.
Pubblicazione: (2024)

Towards Cognitive AI Systems: a Survey and Prospective on Neuro-Symbolic AI
di: Wan, Zishen, et al.
Pubblicazione: (2024)

Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation
di: Pinckney, Nathaniel, et al.
Pubblicazione: (2024)

VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation
di: Tan, Yan, et al.
Pubblicazione: (2026)

CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generation
di: Mi, Zhendong, et al.
Pubblicazione: (2024)

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation
di: Chang, Kaiyan, et al.
Pubblicazione: (2024)

Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
di: Yao, Bingkun, et al.
Pubblicazione: (2024)

The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generation
di: Yang, Guang, et al.
Pubblicazione: (2025)

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting
di: Shahidzadeh, Mohammad, et al.
Pubblicazione: (2024)

Exploring the Agentic Frontier of Verilog Code Generation
di: Yubeaton, Patrick, et al.
Pubblicazione: (2026)

ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
di: Chen, Zhirong, et al.
Pubblicazione: (2025)

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
di: Hemadri, Raghu Vamshi, et al.
Pubblicazione: (2025)

DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base
di: Ibnat, Zahin, et al.
Pubblicazione: (2025)

Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture
di: Wan, Zishen, et al.
Pubblicazione: (2024)

VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
di: Wang, Ning, et al.
Pubblicazione: (2025)

VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
di: Roy, Prithwish Basu, et al.
Pubblicazione: (2026)

Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT
di: Vitolo, Paola, et al.
Pubblicazione: (2024)

GauRast: Enhancing GPU Triangle Rasterizers to Accelerate 3D Gaussian Splatting
di: Li, Sixu, et al.
Pubblicazione: (2025)

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs
di: Jin, Pengwei, et al.
Pubblicazione: (2025)

2-in-1 Accelerator: Enabling Random Precision Switch for Winning Both Adversarial Robustness and Efficiency
di: Fu, Yonggan, et al.
Pubblicazione: (2021)

SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip
di: Hu, Ziteng, et al.
Pubblicazione: (2025)

VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
di: Niu, Juxin, et al.
Pubblicazione: (2025)

GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design
di: You, Haoran, et al.
Pubblicazione: (2021)

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems
di: Yu, Zhongzhi, et al.
Pubblicazione: (2025)

QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation
di: Zhu, Yaoyu, et al.
Pubblicazione: (2025)