Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures
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arXiv
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| Autores principales: | , , , , , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2024
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| _version_ | 1866929410392719360 |
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| author | Zuckerman, Joseph Wellman, John-David Vanamali, Ajay Shankar, Manish Tombesi, Gabriele Swaminathan, Karthik Lee, Kevin Kapur, Mohit Philhower, Robert Bose, Pradip Carloni, Luca P. |
| author_facet | Zuckerman, Joseph Wellman, John-David Vanamali, Ajay Shankar, Manish Tombesi, Gabriele Swaminathan, Karthik Lee, Kevin Kapur, Mohit Philhower, Robert Bose, Pradip Carloni, Luca P. |
| contents | We present several enhancements to the open-source ESP platform to support flexible and efficient on-chip communication for programmable accelerators in heterogeneous SoCs. These enhancements include 1) a flexible point-to-point communication mechanism between accelerators, 2) a multicast NoC that supports data forwarding to multiple accelerators simultaneously, 3) accelerator synchronization leveraging the SoC's coherence protocol, 4) an accelerator interface that offers fine-grained control over the communication mode used, and 5) an example ISA extension to support our enhancements. Our solution adds negligible area to the SoC architecture and requires minimal changes to the accelerators themselves. We have validated most of these features in complex FPGA prototypes and plan to include them in the open-source release of ESP in the coming months. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2407_04182 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures Zuckerman, Joseph Wellman, John-David Vanamali, Ajay Shankar, Manish Tombesi, Gabriele Swaminathan, Karthik Lee, Kevin Kapur, Mohit Philhower, Robert Bose, Pradip Carloni, Luca P. Hardware Architecture We present several enhancements to the open-source ESP platform to support flexible and efficient on-chip communication for programmable accelerators in heterogeneous SoCs. These enhancements include 1) a flexible point-to-point communication mechanism between accelerators, 2) a multicast NoC that supports data forwarding to multiple accelerators simultaneously, 3) accelerator synchronization leveraging the SoC's coherence protocol, 4) an accelerator interface that offers fine-grained control over the communication mode used, and 5) an example ISA extension to support our enhancements. Our solution adds negligible area to the SoC architecture and requires minimal changes to the accelerators themselves. We have validated most of these features in complex FPGA prototypes and plan to include them in the open-source release of ESP in the coming months. |
| title | Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2407.04182 |