Harnessing Integrated CPU-GPU System Memory for HPC: a first look into Grace Hopper
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arXiv
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| Autori principali: | , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866917718365569024 |
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| author | Schieffer, Gabin Wahlgren, Jacob Ren, Jie Faj, Jennifer Peng, Ivy |
| author_facet | Schieffer, Gabin Wahlgren, Jacob Ren, Jie Faj, Jennifer Peng, Ivy |
| contents | Memory management across discrete CPU and GPU physical memory is traditionally achieved through explicit GPU allocations and data copy or unified virtual memory. The Grace Hopper Superchip, for the first time, supports an integrated CPU-GPU system page table, hardware-level addressing of system allocated memory, and cache-coherent NVLink-C2C interconnect, bringing an alternative solution for enabling a Unified Memory system. In this work, we provide the first in-depth study of the system memory management on the Grace Hopper Superchip, in both in-memory and memory oversubscription scenarios. We provide a suite of six representative applications, including the Qiskit quantum computing simulator, using system memory and managed memory. Using our memory utilization profiler and hardware counters, we quantify and characterize the impact of the integrated CPU-GPU system page table on GPU applications. Our study focuses on first-touch policy, page table entry initialization, page sizes, and page migration. We identify practical optimization strategies for different access patterns. Our results show that as a new solution for unified memory, the system-allocated memory can benefit most use cases with minimal porting efforts. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2407_07850 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Harnessing Integrated CPU-GPU System Memory for HPC: a first look into Grace Hopper Schieffer, Gabin Wahlgren, Jacob Ren, Jie Faj, Jennifer Peng, Ivy Distributed, Parallel, and Cluster Computing Memory management across discrete CPU and GPU physical memory is traditionally achieved through explicit GPU allocations and data copy or unified virtual memory. The Grace Hopper Superchip, for the first time, supports an integrated CPU-GPU system page table, hardware-level addressing of system allocated memory, and cache-coherent NVLink-C2C interconnect, bringing an alternative solution for enabling a Unified Memory system. In this work, we provide the first in-depth study of the system memory management on the Grace Hopper Superchip, in both in-memory and memory oversubscription scenarios. We provide a suite of six representative applications, including the Qiskit quantum computing simulator, using system memory and managed memory. Using our memory utilization profiler and hardware counters, we quantify and characterize the impact of the integrated CPU-GPU system page table on GPU applications. Our study focuses on first-touch policy, page table entry initialization, page sizes, and page migration. We identify practical optimization strategies for different access patterns. Our results show that as a new solution for unified memory, the system-allocated memory can benefit most use cases with minimal porting efforts. |
| title | Harnessing Integrated CPU-GPU System Memory for HPC: a first look into Grace Hopper |
| topic | Distributed, Parallel, and Cluster Computing |
| url | https://arxiv.org/abs/2407.07850 |