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| Main Authors: | , , , |
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| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2407.09980 |
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| _version_ | 1866916322748661760 |
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| author | Bagheralmoosavi, Bahareh Fatemieh, Seyed Erfan Reshadinezhad, Mohammad Reza Rubio, Antonio |
| author_facet | Bagheralmoosavi, Bahareh Fatemieh, Seyed Erfan Reshadinezhad, Mohammad Reza Rubio, Antonio |
| contents | The data transfer between a processor and memory has become a design bottleneck in data-intensive applications. Processing-In-Memory (PIM) is a practical approach to overcome the memory wall bottleneck. The 4:2 compressor is suitable for implementing the processor's crucial arithmetic circuits, including multiplier. Some area-efficient memristive structures, like Material Implication (IMPLY) in serial architecture, are compatible with the crossbar array. This paper proposes a serial memristive IMPLY-based 4:2 compressor, which is applied to present new 4-bit and 8-bit multipliers. The proposed circuits are evaluated regarding latency, area, and energy consumption. Compared to the existing serial compressor, the proposed 4:2 compressor's algorithm improves the area, energy consumption, and speed by 36%, 17%, and 15%, respectively. The proposed 4-bit and 8-bit multipliers are improved by 7.3% and 10%, respectively, regarding the latency, and reduced energy consumption by up to 12%, compared to the serial multiplier based on a 4:2 compressor with XOR/MUX design. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2407_09980 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Power-Area Efficient Serial IMPLY-based 4:2 Compressor Applied in Data-Intensive Applications Bagheralmoosavi, Bahareh Fatemieh, Seyed Erfan Reshadinezhad, Mohammad Reza Rubio, Antonio Emerging Technologies Hardware Architecture The data transfer between a processor and memory has become a design bottleneck in data-intensive applications. Processing-In-Memory (PIM) is a practical approach to overcome the memory wall bottleneck. The 4:2 compressor is suitable for implementing the processor's crucial arithmetic circuits, including multiplier. Some area-efficient memristive structures, like Material Implication (IMPLY) in serial architecture, are compatible with the crossbar array. This paper proposes a serial memristive IMPLY-based 4:2 compressor, which is applied to present new 4-bit and 8-bit multipliers. The proposed circuits are evaluated regarding latency, area, and energy consumption. Compared to the existing serial compressor, the proposed 4:2 compressor's algorithm improves the area, energy consumption, and speed by 36%, 17%, and 15%, respectively. The proposed 4-bit and 8-bit multipliers are improved by 7.3% and 10%, respectively, regarding the latency, and reduced energy consumption by up to 12%, compared to the serial multiplier based on a 4:2 compressor with XOR/MUX design. |
| title | Power-Area Efficient Serial IMPLY-based 4:2 Compressor Applied in Data-Intensive Applications |
| topic | Emerging Technologies Hardware Architecture |
| url | https://arxiv.org/abs/2407.09980 |