Towards Efficient Design Verification -- Constrained Random Verification using PyUVM
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arXiv
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| Hauptverfasser: | , , |
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| Format: | Preprint |
| Veröffentlicht: |
2024
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| _version_ | 1866913430635544576 |
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| author | Gadde, Deepak Narayan Kumari, Suruchi Kumar, Aman |
| author_facet | Gadde, Deepak Narayan Kumari, Suruchi Kumar, Aman |
| contents | Python, as a multi-paradigm language known for its ease of integration with other languages, has gained significant attention among verification engineers recently. A Python-based verification environment capitalizes on open-source frameworks such as PyUVM providing Python-based UVM 1.2 implementation and PyVSC facilitating constrained randomization and functional coverage. These libraries play a pivotal role in expediting test development and hold promise for reducing setup costs. The goal of this paper is to evaluate the effectiveness of PyUVM verification testbenches across various design IPs, aiming for a comprehensive comparison of their features and performance metrics with the established SystemVerilog-UVM methodology. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2407_10317 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Towards Efficient Design Verification -- Constrained Random Verification using PyUVM Gadde, Deepak Narayan Kumari, Suruchi Kumar, Aman Hardware Architecture Python, as a multi-paradigm language known for its ease of integration with other languages, has gained significant attention among verification engineers recently. A Python-based verification environment capitalizes on open-source frameworks such as PyUVM providing Python-based UVM 1.2 implementation and PyVSC facilitating constrained randomization and functional coverage. These libraries play a pivotal role in expediting test development and hold promise for reducing setup costs. The goal of this paper is to evaluate the effectiveness of PyUVM verification testbenches across various design IPs, aiming for a comprehensive comparison of their features and performance metrics with the established SystemVerilog-UVM methodology. |
| title | Towards Efficient Design Verification -- Constrained Random Verification using PyUVM |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2407.10317 |