StoX-Net: Stochastic Processing of Partial Sums for Efficient In-Memory Computing DNN Accelerators
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arXiv
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| Autori principali: | , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866910688914440192 |
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| author | Rogers, Ethan G Mugdho, Sohan Salahuddin Gupte, Kshemal Kshemendra Wang, Cheng |
| author_facet | Rogers, Ethan G Mugdho, Sohan Salahuddin Gupte, Kshemal Kshemendra Wang, Cheng |
| contents | Crossbar-based in-memory computing (IMC) has emerged as a promising platform for hardware acceleration of deep neural networks (DNNs). However, the energy and latency of IMC systems are dominated by the large overhead of the peripheral analog-to-digital converters (ADCs). To address such ADC bottleneck, here we propose to implement stochastic processing of array-level partial sums (PS) for efficient IMC. Leveraging the probabilistic switching of spin-orbit torque magnetic tunnel junctions, the proposed PS processing eliminates the costly ADC, achieving significant improvement in energy and area efficiency. To mitigate accuracy loss, we develop PS-quantization-aware training that enables backward propagation across stochastic PS. Furthermore, a novel scheme with an inhomogeneous sampling length of the stochastic conversion is proposed. When running ResNet20 on the CIFAR-10 dataset, our architecture-to-algorithm co-design demonstrates up to 16x, 8x, and 10x improvement in energy, latency, and area, respectively, compared to IMC with standard ADC. Our optimized design configuration using stochastic PS achieved 130x (24x) improvement in Energy-Delay-Product compared to IMC with full precision ADC (sparse low-bit ADC), while maintaining near-software accuracy at various benchmark classification tasks. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2407_12378 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | StoX-Net: Stochastic Processing of Partial Sums for Efficient In-Memory Computing DNN Accelerators Rogers, Ethan G Mugdho, Sohan Salahuddin Gupte, Kshemal Kshemendra Wang, Cheng Hardware Architecture Artificial Intelligence Emerging Technologies Crossbar-based in-memory computing (IMC) has emerged as a promising platform for hardware acceleration of deep neural networks (DNNs). However, the energy and latency of IMC systems are dominated by the large overhead of the peripheral analog-to-digital converters (ADCs). To address such ADC bottleneck, here we propose to implement stochastic processing of array-level partial sums (PS) for efficient IMC. Leveraging the probabilistic switching of spin-orbit torque magnetic tunnel junctions, the proposed PS processing eliminates the costly ADC, achieving significant improvement in energy and area efficiency. To mitigate accuracy loss, we develop PS-quantization-aware training that enables backward propagation across stochastic PS. Furthermore, a novel scheme with an inhomogeneous sampling length of the stochastic conversion is proposed. When running ResNet20 on the CIFAR-10 dataset, our architecture-to-algorithm co-design demonstrates up to 16x, 8x, and 10x improvement in energy, latency, and area, respectively, compared to IMC with standard ADC. Our optimized design configuration using stochastic PS achieved 130x (24x) improvement in Energy-Delay-Product compared to IMC with full precision ADC (sparse low-bit ADC), while maintaining near-software accuracy at various benchmark classification tasks. |
| title | StoX-Net: Stochastic Processing of Partial Sums for Efficient In-Memory Computing DNN Accelerators |
| topic | Hardware Architecture Artificial Intelligence Emerging Technologies |
| url | https://arxiv.org/abs/2407.12378 |