SigDLA: A Deep Learning Accelerator Extension for Signal Processing
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arXiv
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| Main Authors: | , , , , , , , , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866910531429859328 |
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| author | Fu, Fangfa Zhang, Wenyu Jiang, Zesong Zhu, Zhiyu Li, Guoyu Yang, Bing Liu, Cheng Xiao, Liyi Wang, Jinxiang Li, Huawei Li, Xiaowei |
| author_facet | Fu, Fangfa Zhang, Wenyu Jiang, Zesong Zhu, Zhiyu Li, Guoyu Yang, Bing Liu, Cheng Xiao, Liyi Wang, Jinxiang Li, Huawei Li, Xiaowei |
| contents | Deep learning and signal processing are closely correlated in many IoT scenarios such as anomaly detection to empower intelligence of things. Many IoT processors utilize digital signal processors (DSPs) for signal processing and build deep learning frameworks on this basis. While deep learning is usually much more computing-intensive than signal processing, the computing efficiency of deep learning on DSPs is limited due to the lack of native hardware support. In this case, we present a contrary strategy and propose to enable signal processing on top of a classical deep learning accelerator (DLA). With the observation that irregular data patterns such as butterfly operations in FFT are the major barrier that hinders the deployment of signal processing on DLAs, we propose a programmable data shuffling fabric and have it inserted between the input buffer and computing array of DLAs such that the irregular data is reorganized and the processing is converted to be regular. With the online data shuffling, the proposed architecture, SigDLA, can adapt to various signal processing tasks without affecting the deep learning processing. Moreover, we build a reconfigurable computing array to suit the various data width requirements of both signal processing and deep learning. According to our experiments, SigDLA achieves an average performance speedup of 4.4$\times$, 1.4$\times$, and 1.52$\times$, and average energy reduction of 4.82$\times$, 3.27$\times$, and 2.15$\times$ compared to an embedded ARM processor with customized DSP instructions, a DSP processor, and an independent DSP-DLA architecture respectively with 17% more chip area over the original DLAs. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2407_12565 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | SigDLA: A Deep Learning Accelerator Extension for Signal Processing Fu, Fangfa Zhang, Wenyu Jiang, Zesong Zhu, Zhiyu Li, Guoyu Yang, Bing Liu, Cheng Xiao, Liyi Wang, Jinxiang Li, Huawei Li, Xiaowei Hardware Architecture Deep learning and signal processing are closely correlated in many IoT scenarios such as anomaly detection to empower intelligence of things. Many IoT processors utilize digital signal processors (DSPs) for signal processing and build deep learning frameworks on this basis. While deep learning is usually much more computing-intensive than signal processing, the computing efficiency of deep learning on DSPs is limited due to the lack of native hardware support. In this case, we present a contrary strategy and propose to enable signal processing on top of a classical deep learning accelerator (DLA). With the observation that irregular data patterns such as butterfly operations in FFT are the major barrier that hinders the deployment of signal processing on DLAs, we propose a programmable data shuffling fabric and have it inserted between the input buffer and computing array of DLAs such that the irregular data is reorganized and the processing is converted to be regular. With the online data shuffling, the proposed architecture, SigDLA, can adapt to various signal processing tasks without affecting the deep learning processing. Moreover, we build a reconfigurable computing array to suit the various data width requirements of both signal processing and deep learning. According to our experiments, SigDLA achieves an average performance speedup of 4.4$\times$, 1.4$\times$, and 1.52$\times$, and average energy reduction of 4.82$\times$, 3.27$\times$, and 2.15$\times$ compared to an embedded ARM processor with customized DSP instructions, a DSP processor, and an independent DSP-DLA architecture respectively with 17% more chip area over the original DLAs. |
| title | SigDLA: A Deep Learning Accelerator Extension for Signal Processing |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2407.12565 |