HENNC: Hardware Engine for Artificial Neural Network-based Chaotic Oscillators
Fuente:
arXiv
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| Autores principales: | , , , |
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| Formato: | Preprint |
| Publicado: |
2024
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| Materias: | |
| Acceso en línea: | |
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| _version_ | 1866929439035621376 |
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| author | Vaziri, Mobin Vakili, Shervin Rahimifar, M. Mehdi Langlois, J. M. Pierre |
| author_facet | Vaziri, Mobin Vakili, Shervin Rahimifar, M. Mehdi Langlois, J. M. Pierre |
| contents | This letter introduces a framework for the automatic generation of hardware cores for Artificial Neural Network (ANN)-based chaotic oscillators. The framework trains the model to approximate a chaotic system, then performs design space exploration yielding potential hardware architectures for its implementation. The framework then generates the corresponding synthesizable High-Level Synthesis code and a validation testbench from a selected solution. The hardware design primarily targets FPGAs. The proposed framework offers a rapid hardware design process of candidate architectures superior to manually designed works in terms of hardware cost and throughput. The source code is available on GitHub. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2407_19165 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | HENNC: Hardware Engine for Artificial Neural Network-based Chaotic Oscillators Vaziri, Mobin Vakili, Shervin Rahimifar, M. Mehdi Langlois, J. M. Pierre Hardware Architecture Neural and Evolutionary Computing This letter introduces a framework for the automatic generation of hardware cores for Artificial Neural Network (ANN)-based chaotic oscillators. The framework trains the model to approximate a chaotic system, then performs design space exploration yielding potential hardware architectures for its implementation. The framework then generates the corresponding synthesizable High-Level Synthesis code and a validation testbench from a selected solution. The hardware design primarily targets FPGAs. The proposed framework offers a rapid hardware design process of candidate architectures superior to manually designed works in terms of hardware cost and throughput. The source code is available on GitHub. |
| title | HENNC: Hardware Engine for Artificial Neural Network-based Chaotic Oscillators |
| topic | Hardware Architecture Neural and Evolutionary Computing |
| url | https://arxiv.org/abs/2407.19165 |