ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors

Fuente: arXiv

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Bibliographic Details
Main Authors:	Gajaria, Dhruv, Adegbija, Tosiron
Format:	Preprint
Published:	2024
Subjects:	Computers and Society Hardware Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2407.19612