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ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors

Fuente: arXiv

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Detalles Bibliográficos
Autores principales:	Gajaria, Dhruv, Adegbija, Tosiron
Formato:	Preprint
Publicado:	2024
Materias:	Computers and Society Hardware Architecture
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

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