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| Main Authors: | , , , , , , , , |
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| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2407.19895 |
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| _version_ | 1866917746103549952 |
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| author | Tedeschi, Riccardo Valente, Luca Ottavi, Gianmarco Zelioli, Enrico Wistoff, Nils Giacometti, Massimiliano Sajjad, Abdul Basit Benini, Luca Rossi, Davide |
| author_facet | Tedeschi, Riccardo Valente, Luca Ottavi, Gianmarco Zelioli, Enrico Wistoff, Nils Giacometti, Massimiliano Sajjad, Abdul Basit Benini, Luca Rossi, Davide |
| contents | Symmetric Multi-Processing (SMP) based on cache coherency is crucial for high-end embedded systems like automotive applications. RISC-V is gaining traction, and open-source hardware (OSH) platforms offer solutions to issues such as IP costs and vendor dependency. Existing multi-core cache-coherent RISC-V platforms are complex and not efficient for small embedded core clusters. We propose an open-source SystemVerilog implementation of a lightweight snoop-based cache-coherent cluster of Linux-capable CVA6 cores. Our design uses the MOESI protocol via the Arm's AMBA ACE protocol. Evaluated with Splash-3 benchmarks, our solution shows up to 32.87% faster performance in a dual-core setup and an average improvement of 15.8% over OpenPiton. Synthesized using GF 22nm FDSOI technology, the Cache Coherency Unit occupies only 1.6% of the system area. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2407_19895 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor Tedeschi, Riccardo Valente, Luca Ottavi, Gianmarco Zelioli, Enrico Wistoff, Nils Giacometti, Massimiliano Sajjad, Abdul Basit Benini, Luca Rossi, Davide Systems and Control Symmetric Multi-Processing (SMP) based on cache coherency is crucial for high-end embedded systems like automotive applications. RISC-V is gaining traction, and open-source hardware (OSH) platforms offer solutions to issues such as IP costs and vendor dependency. Existing multi-core cache-coherent RISC-V platforms are complex and not efficient for small embedded core clusters. We propose an open-source SystemVerilog implementation of a lightweight snoop-based cache-coherent cluster of Linux-capable CVA6 cores. Our design uses the MOESI protocol via the Arm's AMBA ACE protocol. Evaluated with Splash-3 benchmarks, our solution shows up to 32.87% faster performance in a dual-core setup and an average improvement of 15.8% over OpenPiton. Synthesized using GF 22nm FDSOI technology, the Cache Coherency Unit occupies only 1.6% of the system area. |
| title | Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor |
| topic | Systems and Control |
| url | https://arxiv.org/abs/2407.19895 |