Configurable Multi-Port Memory Architecture for High-Speed Data Communication
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arXiv
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| Auteurs principaux: | , |
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| Format: | Preprint |
| Publié: |
2024
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| _version_ | 1866917830121750528 |
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| author | Dhakad, Narendra Singh Vishvakarma, Santosh Kumar |
| author_facet | Dhakad, Narendra Singh Vishvakarma, Santosh Kumar |
| contents | Memory management is necessary with the increasing number of multi-connected AI devices and data bandwidth issues. For this purpose, high-speed multi-port memory is used. The traditional multi-port memory solutions are hard-bounded to a fixed number of ports for read or write operations. In this work, we proposed a pseudo-quad-port memory architecture. Here, ports can be configured (1-port, 2-port, 3-port, 4-port) for all possible combinations of read/write operations for the 6T static random access memory (SRAM) memory array, which improves the speed and reduces the bandwidth for data transfer. The proposed architecture improves the bandwidth of data transfer by 4x. The proposed solution provides 1.3x and 2x area efficiency as compared to dual-port 8T and quad-port 12T SRAM. All the design and performance analyses are done using 65nm CMOS technology. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2407_20628 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Configurable Multi-Port Memory Architecture for High-Speed Data Communication Dhakad, Narendra Singh Vishvakarma, Santosh Kumar Hardware Architecture Memory management is necessary with the increasing number of multi-connected AI devices and data bandwidth issues. For this purpose, high-speed multi-port memory is used. The traditional multi-port memory solutions are hard-bounded to a fixed number of ports for read or write operations. In this work, we proposed a pseudo-quad-port memory architecture. Here, ports can be configured (1-port, 2-port, 3-port, 4-port) for all possible combinations of read/write operations for the 6T static random access memory (SRAM) memory array, which improves the speed and reduces the bandwidth for data transfer. The proposed architecture improves the bandwidth of data transfer by 4x. The proposed solution provides 1.3x and 2x area efficiency as compared to dual-port 8T and quad-port 12T SRAM. All the design and performance analyses are done using 65nm CMOS technology. |
| title | Configurable Multi-Port Memory Architecture for High-Speed Data Communication |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2407.20628 |