Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic
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arXiv
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| Hauptverfasser: | , , , |
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| Format: | Preprint |
| Veröffentlicht: |
2024
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| _version_ | 1866910549001895936 |
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| author | Volk, Jennifer Papanikolaou, Panagiotis Zervakis, Georgios Tzimpragos, Georgios |
| author_facet | Volk, Jennifer Papanikolaou, Panagiotis Zervakis, Georgios Tzimpragos, Georgios |
| contents | Gate-level clocking, typical in traditional approaches to Single Flux Quantum (SFQ) technology, makes the effective synthesis of superconducting circuits a significant engineering hurdle. This paper addresses this challenge by employing the recently introduced alternating SFQ (xSFQ) logic family. xSFQ leverages dual-rail alternating encoding to eliminate the clock dependency from the superconducting gate semantics. This obviates the need for ad hoc modifications to existing synthesis tools and avoids unnecessary circuit resource overheads, marking a significant advancement in superconducting circuit design automation. Our implementation results demonstrate an average reduction of over 80\% in the Josephson junction count for circuits from the ISCAS85, EPFL, and ISCAS89 benchmark suites. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2407_20942 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic Volk, Jennifer Papanikolaou, Panagiotis Zervakis, Georgios Tzimpragos, Georgios Hardware Architecture Gate-level clocking, typical in traditional approaches to Single Flux Quantum (SFQ) technology, makes the effective synthesis of superconducting circuits a significant engineering hurdle. This paper addresses this challenge by employing the recently introduced alternating SFQ (xSFQ) logic family. xSFQ leverages dual-rail alternating encoding to eliminate the clock dependency from the superconducting gate semantics. This obviates the need for ad hoc modifications to existing synthesis tools and avoids unnecessary circuit resource overheads, marking a significant advancement in superconducting circuit design automation. Our implementation results demonstrate an average reduction of over 80\% in the Josephson junction count for circuits from the ISCAS85, EPFL, and ISCAS89 benchmark suites. |
| title | Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2407.20942 |