Functional ISS-Driven Verification of Superscalar RISC-V Processors
Fuente:
arXiv
Salvato in:
| Autori principali: | , , , |
|---|---|
| Natura: | Preprint |
| Pubblicazione: |
2024
|
| Soggetti: | |
| Accesso online: | |
| Tags: |
Aggiungi Tag
Nessun Tag, puoi essere il primo ad aggiungerne!!
|
| _version_ | 1866913669150932992 |
|---|---|
| author | Galimberti, Andrea Vitali, Marco Vittoria, Sebastiano Zoni, Davide |
| author_facet | Galimberti, Andrea Vitali, Marco Vittoria, Sebastiano Zoni, Davide |
| contents | A time-efficient and comprehensive verification is a fundamental part of the design process for modern computing platforms, and it becomes ever more important and critical to optimize as the latter get ever more complex. SupeRFIVe is a methodology for the functional verification of superscalar processors that leverages an instruction set simulator to validate their correctness according to a simulation-based approach, interfacing a testbench for the design under test with the instruction set simulator by means of socket communication. We demonstrate the effectiveness of the SupeRFIVe methodology by applying it to verify the functional correctness of a RISC-V dual-issue superscalar CPU, leveraging the state-of-the-art RISC-V instruction set simulator Spike and executing a set of benchmark applications from the open literature. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2407_21192 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Functional ISS-Driven Verification of Superscalar RISC-V Processors Galimberti, Andrea Vitali, Marco Vittoria, Sebastiano Zoni, Davide Hardware Architecture A time-efficient and comprehensive verification is a fundamental part of the design process for modern computing platforms, and it becomes ever more important and critical to optimize as the latter get ever more complex. SupeRFIVe is a methodology for the functional verification of superscalar processors that leverages an instruction set simulator to validate their correctness according to a simulation-based approach, interfacing a testbench for the design under test with the instruction set simulator by means of socket communication. We demonstrate the effectiveness of the SupeRFIVe methodology by applying it to verify the functional correctness of a RISC-V dual-issue superscalar CPU, leveraging the state-of-the-art RISC-V instruction set simulator Spike and executing a set of benchmark applications from the open literature. |
| title | Functional ISS-Driven Verification of Superscalar RISC-V Processors |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2407.21192 |